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PIC24F Family Reference Manual
DS39737A-page 49-38 Preliminary © 2010 Microchip Technology Inc.
49.9.2 A/D Conversions While Scanning Through All Analog Inputs
Figure 49-20 and Table 49-13 illustrate a typical setup where all available analog input channels
are sampled by one S&H channel, CH0, and converted. The Set Scan Input Selection bit
(CSCNA) in the ADC Control Register 2 (ADxCON2<10>) specifies scanning of the ADC inputs
to the CH0 positive input. Other conditions are similar to those described in Section 49.9.1
“Sampling and Converting a Single Channel Multiple Times”.
Initially, the AN0 input is sampled by CH0 and converted, and then the AN1 input is sampled and
converted. This process of scanning the inputs repeats 6 times until the buffer is full. The result
is stored in the ADC buffer (ADC1BUF0-ADC1BUF5), and then the ADC module generates an
interrupt. The entire process then repeats.
Figure 49-20: Scanning Through 16 Inputs/Interrupt
ADC Clock
SAMP
ADC1BUF0
TSAMP
TCONV
ADC1BUF1
DONE
ADC1BUF2
ADC1BUF5
Input to CH0
AN0
TSAMP
TCONV
AN1
TSAMP
TCONV
AN4
TSAMP
TCONV
AN5
AD1IF
ASAM
Conversion
Trigger

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