Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-20
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
23.3.4.3 SPI MASTER MODE AND FRAME MASTER MODE
In Master/Frame Master mode, the SPIx module generates both the clock and frame synchroni-
zation signals, as shown in Figure 23-9. It is enabled by setting the MSTEN and FRMEN bits to
‘1’ and the SPIFSD bit to ‘0’.
In this mode, the serial clock is output continuously at the SCKx pin, regardless of whether the
module is transmitting. When SPIxBUF is written, the SSx
pin will be driven to its active state (as
determined by the SPIFPOL bit) on the appropriate transmit edge of the SCKx clock, and remain
active for one data frame. If the SPIFE control bit (SPIxCON2<1>) is cleared, the frame sync
pulse precedes the data transmission, as shown in Figure 23-10. If SPIFE is set, the frame sync
pulse coincides with the beginning of the data transmission, as shown in Figure 23-11. The mod-
ule starts transmitting data on the next transmit edge of the SCKx.
Figure 23-9: SPI Master, Frame Master Connection Diagram
Figure 23-10: SPI Master, Frame Master Timing (SPIFE = 0)
Figure 23-11: SPI Master, Frame Master Timing (SPIFE = 1)
SDOx
SDIx
PIC24F
Serial Clock
SSx
SCKx
Frame Sync
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPI Slave, Frame Slave)
SCKx
SSx
SDOx
(CKP = 0)
Bit 14 Bit 13 Bit 12
SDIx
Bit 14 Bit 13 Bit 12
Write to SPIxBUF
Receive Samples at SDIx
Pulse Generated at SSx
SCKx
(CKP = 1)
(SPIFPOL=1)
SSx
(SPIFPOL=0)
Bit 15
Bit 15
SCKx
SDOx
(CKP = 0)
Bit 14 Bit 13 Bit 12
SDIx
Bit 14 Bit 13 Bit 12
Write to SPIxBUF
Pulse Generated by SSx,
SCKx
(CKP = 1)
SSx
(SPIFPOL=1)
SSx
(SPIFPOL=0)
Receive Samples at SDIx
Bit 15
Bit 15
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section23-Serial_Peripheral_Interface.pdf