Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 24 2014 Microchip Technology Inc.
The buffer overflow event, when the SPIROV bit is set, can corrupt the FIFO Pointers and status
bits of the SPIx module. To recover from an overflow, the SPIx module has to be disabled
(SPIEN = 0) and then re-enabled (SPIEN = 1).
The timing of events in Enhanced Buffer Master mode operation is essentially the same as that
for Standard Master mode, as shown in Figure 3-2.
The following procedure is used to set up the SPIx module for the Enhanced Buffer Master mode
of operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx register.
b) Select an Interrupt mode using the SISEL<2:0> bits (SPIxSTAT<4:2>).
c) Set the SPIxIE bit in the respective IECx register.
d) Write the SPIxIP bits in the respective IPCx register.
2. When MSTEN (SPIxCON1<5>) = 1, write the desired settings to the SPIxCON1 and
SPIxCON2 registers.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>).
5. Enable the SPIx operation by setting the SPIEN bit (SPIxSTAT<15>).
6. Write the data to be transmitted to the SPIxBUF register. The transmission (and reception)
starts as soon as data is written to the SPIxBUF register.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf