Vault 7: Projects
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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 226 © 2005-2011 Microchip Technology Inc.
DIV.U
Unsigned Integer Divide
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} DIV.U{W} Wm, Wn
DIV.UD Wm, Wn
Operands: Wm ∈ [ W0 ... W15] for word operation
Wm ∈ [ W0, W2, W4 ... W14] for double operation
Wn ∈ [ W2 ... W15]
Operation: For word operation (default):
Wm → W0
0x0 →W1
W1:W0/Wn → W0
Remainder → W1
For double operation (DIV.UD):
Wm + 1:Wm → W1:W0
W1:W0/Wns → W0
Remainder →W1
Status Affected: N, OV, Z, C
Encoding: 1101 1000 1ttt tvvv vW00 ssss
Description: Iterative, unsigned integer divide, where the dividend is stored in Wm (for
a 16-bit by 16-bit divide), or Wm + 1:Wm (for a 32-bit by 16-bit divide) and
the divisor is stored in Wn. In the word operation, Wm is first copied to W0
and W1 is cleared to perform the divide. In the double operation,
Wm + 1:Wm is first copied to W1:W0. The 16-bit quotient of the divide
operation is stored in W0, and the 16-bit remainder is stored in W1.
This instruction must be executed 18 times using the REPEAT instruction
(with an iteration count of 17) to generate the correct quotient and
remainder. The N flag will always be cleared. The OV flag will be set if the
divide operation resulted in an overflow and cleared otherwise. The Z flag
will be set if the remainder is ‘0’ and cleared otherwise. The C flag is used
to implement the divide algorithm and its final value should not be used.
The ‘t’ bits select the most significant word of the dividend for the double
operation. These bits are clear for the word operation.
The ‘v’ bits select the least significant word of the dividend.
The ‘W’ bit selects the dividend size (‘0’ for 16-bit, ‘1’ for 32-bit).
The ‘s’ bits select the divisor register.
Note 1: The extension .D in the instruction denotes a double word
(32-bit) dividend rather than a word dividend. You may use a
.W extension to denote a word operation, but it is not required.
2: Unexpected results will occur if the quotient can not be
represented in 16 bits. This may only occur for the double
operation (DIV.UD). When an overflow occurs, the OV Status
bit will be set and the quotient and remainder should not be
used.
3: Dividing by zero will initiate an arithmetic error trap during the
first cycle of execution.
4: This instruction is interruptible on each instruction cycle
boundary.
Words: 1
Cycles: 18 (plus 1 for REPEAT execution)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf