Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 18 2014 Microchip Technology Inc.
3.3.2.2 Slave Select Synchronization
The SSx pin allows Synchronous Slave mode. If the Slave Select Enable bit (SSEN) is set
(SPIxCON1<7> = 1), transmission and reception are enabled in Slave mode only if the SSx
pin
is driven to a low state (see Figure 3-4). The port output or other peripheral outputs must not be
driven in order to allow the SSx pin to function as an input. If the SSEN bit is set and the SSx pin
is driven high, the SDOx pin is no longer driven and will tri-state, even if the module is in the
middle of a transmission.
An aborted transmission is retried when the SSx
pin is driven low again using the data held in
the SPIxTXB register. If the SSEN bit is not set, the SSx
pin does not affect the module operation
in Slave mode.
3.3.2.3 SPITBF Status Flag Operation
The SPITBF bit in the SPIxSTAT register (SPIxSTAT<1>) functions differently in Slave mode than
it does in Master mode.
If the SSEN bit is cleared (SPIxCON1<7> = 0), the SPITBF bit is set when the SPIxBUF
register is loaded by the user application. It is cleared when the module transfers data from
the SPIxTXB register to the SPIxSR register. This is similar to the SPITBF bit function in
Master mode.
If the SSEN bit is set (SPIxCON1<7> = 1), the SPITBF bit is set when the SPIxBUF register
is loaded by the user application. However, it is cleared only when the SPIx module
completes the data transmission. The transmission is aborted when the SSx
pin goes high.
Each data word is held in the SPIxTXB register until all bits are transmitted to the receiver.
Note: To meet the module timing requirements, the SSx
pin must be enabled in Slave
mode when CKE = 1 (see Figure 3-5).

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