Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 84 © 2005-2011 Microchip Technology Inc.
4.13 ACCUMULATOR ACCESS (dsPIC30F, dsPIC33F AND dsPIC33E DEVICES)
The six registers of Accumulator A and Accumulator B are memory mapped like any other
Special Function Register. This feature allows them to be accessed with file register or indirect
addressing, using any instruction which supports such addressing. However, it is recommended
that the DSP instructions LAC, SAC and SAC.R be used to load and store the accumulators,
since they provide sign-extension, shifting and rounding capabilities. LAC, SAC and SAC.R
instruction details are provided in
Section 5. “Instruction Descriptions”.
4.14 DSP MAC INSTRUCTIONS (dsPIC30F, dsPIC33F AND dsPIC33E DEVICES)
The DSP Multiply and Accumulate (MAC) operations are a special suite of instructions which
provide the most efficient use of the dsPIC30F, dsPIC33F, and dsPIC33E architectures. The DSP
MAC instructions, shown in
Table 4-11, utilize both the X and Y data paths of the CPU core, which
enables these instructions to perform the following operations all in one cycle:
two reads from data memory using prefetch working registers (MAC Prefetches)
two updates to prefetch working registers (MAC Prefetch Register Updates)
one mathematical operation with an accumulator (MAC Operations)
In addition, four of the ten DSP MAC instructions are also capable of performing an operation with
one accumulator, while storing out the rounded contents of the alternate accumulator. This
feature is called accumulator Write Back (WB) and it provides flexibility for the software
developer. For instance, the accumulator WB may be used to run two algorithms concurrently, or
efficiently process complex numbers, among other things.
Table 4-11: DSP MAC Instructions
4.14.1 MAC Prefetches
Prefetches (or data reads) are made using the effective address stored in the working register.
The two prefetches from data memory must be specified using the working register assignments
shown in
Table 4-9. One read must occur from the X data bus using W8 or W9, and one read
must occur from the Y data bus using W10 or W11. The allowed destination registers for both
prefetches are W4-W7.
As shown in Table 4-3, one special Addressing mode exists for the MAC class of instructions. This
mode is the Register Offset Addressing mode and utilizes W12. In this mode, the prefetch is
made using the effective address of the specified working register, plus the 16-bit signed value
stored in W12. Register Offset Addressing may only be used in the X space with W9, and in the
Y-space with W11.
Note 1: For convenience, ACCAU and ACCBU are sign-extended to 16 bits. This provides
the flexibility to access these registers using either Byte or Word mode (when file
register or indirect addressing is used).
2: The OA, OB, SA or SB bit cannot be set by writing overflowed values to the memory
mapped accumulators using MOV instructions, as these status bits are only affected
by DSP operations.
Instruction Description Accumulator WB?
CLR Clear accumulator Yes
ED Euclidean distance (no accumulate) No
EDAC Euclidean distance No
MAC Multiply and accumulate Yes
MAC Square and accumulate No
MOVSAC Move from X and Y bus Yes
MPY Multiply to accumulator No
MPY Square to accumulator No
MPY.N Negative multiply to accumulator No
MSC Multiply and subtract Yes

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