Vault 7: Projects
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© 2005-2011 Microchip Technology Inc. DS70157F-page 333
Section 5. Instruction Descriptions
Instruction
Descriptions
5
NEG
Negate f
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} NEG{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: (f)
+ 1 → destination designated by D
Status Affected: DC, N, OV, Z, C
Encoding: 1110 1110 0BDf ffff ffff ffff
Description: Compute the two’s complement of the contents of the file register and
place the result in the destination register. The optional WREG operand
determines the destination register. If WREG is specified, the result is
stored in WREG. If WREG is not specified, the result is stored in the file
register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
NEG.B 0x880, WREG ; Negate (0x880) (Byte mode)
; Store result to WREG
Before
Instruction
After
Instruction
WREG (W0) 9080 WREG (W0) 90AB
Data 0880 2355 Data 0880 2355
SR 0000 SR 0008 (N = 1)
Example 2:
NEG 0x1200 ; Negate (0x1200) (Word mode)
Before
Instruction
After
Instruction
Data 1200 8923 Data 1200 76DD
SR 0000 SR 0000
NEG
Negate Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} NEG{.B} Ws, Wd
[Ws], [Wd]
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf