Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2006 Microchip Technology Inc. Advance Information DS39698A-page 10-5
Section 10. Power-Saving Features
Power-Saving
Features
10
10.3.2 Idle Mode
When the device enters Idle mode, the following events occur:
The CPU will stop executing instructions.
The WDT is automatically cleared.
The system clock source will remain active and peripheral modules, by default, will
continue to operate normally from the system clock source. Peripherals can optionally be
shut down in Idle mode using their ‘Stop in Idle’ control bit. (See peripheral descriptions for
further details.)
If the WDT or FSCM is enabled, the LPRC will also remain active.
The processor will wake from Idle mode on the following events:
On any interrupt that is individually enabled.
On any source of device Reset.
On a WDT time-out.
Upon wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins
immediately, starting with the instruction following the PWRSAV instruction, or the first instruction
in the ISR.
10.3.2.1 WAKE-UP FROM IDLE ON INTERRUPT
User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Idle
mode because the interrupt source is effectively disabled. To use an interrupt as a wake-up
source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater.
Any source of interrupt that is individually enabled, using the corresponding IE control bit in the
IECx register and exceeds the current CPU priority level, will be able to wake-up the processor
from Idle mode. When the device wakes from Idle mode, one of two options may occur:
If the assigned priority for the interrupt is less than or equal to the current CPU priority, the
device will wake-up and continue code execution from the instruction following the PWRSAV
instruction that initiated Idle mode.
If the assigned priority level for the interrupt source is greater than the current CPU priority,
the device will wake-up and the CPU exception process will begin. Code execution will
continue from the first instruction of the ISR.
The IDLE status bit (RCON<2>) is set upon wake-up.
10.3.2.2 WAKE-UP FROM IDLE ON RESET
Any Reset, other than a POR, will wake the CPU from Idle mode. On any device Reset, except
a POR, the IDLE status bit is set (RCON<2>) to indicate that the device was previously in Idle
mode. In a Power-on Reset, the IDLE bit is cleared.
10.3.2.3 WAKE-UP FROM IDLE ON WDT TIME-OUT
If the WDT is enabled, then the processor will wake from Idle mode on a WDT time-out and
continue code execution with the instruction following the PWRSAV instruction that initiated Idle
mode. Note that the WDT time-out does not reset the device in this case. The WDTO and IDLE
status bits (RCON<4,2>) will both be set.
10.3.2.4 TIME DELAYS ON WAKE FROM IDLE MODE
Unlike a wake-up from Sleep mode, there are no time delays associated with wake-up from Idle
mode. The system clock is running during Idle mode, therefore, no start-up times are required at
wake-up.
10.3.3 Interrupts Coincident with Power Save Instructions
Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry
into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode.

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh