Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2007-2014 Microchip Technology Inc. DS70000195F-page 47
Inter-Integrated Circuit™ (I
2
C™)
7.3.8 RECEIVING ALL ADDRESSES (IPMI OPERATION)
Some I
2
C system protocols require a slave to act upon all messages on the bus. For example,
the IPMI bus uses the I
2
C nodes as message repeaters in a distributed network. To allow a node
to repeat all messages, the slave must accept all messages, regardless of the device address.
To enable the IPMI mode, set the IPMIEN bit (I2CxCON<11>) as illustrated in Figure 7-10.
Regardless of the state of the A10M and GCEN bits or the value loaded in the I2CxADD register,
all addresses are accepted. This includes all valid 7-bit addresses, general call, Start byte, Cbus,
reserved and HS modes, and 10-bit address preambles.
Figure 7-10: IPMI Address Detection Timing Diagram (IPMIEN = 1)
SCLx (Master)
SDAx (Master)
SDAx (Slave)
SI2CxIF Interrupt
2 31
Detecting Start bit enables
1
I
2
C™ Bus State (D) (D) (A)(D)
D/A
I2CxRCV
RBF
R/W
address detection.
Regardless of contents, byte
2
address is matched.
Address match clears D/A
status bit.
R/W
status bit is set/clear. Slave
3
generates interrupt.
4
Bus is waiting.
4
Slave generates an ACK. Address
is loaded into I2CxRCV register.
(S) (Q)
R/W
Note: The user application must clear the IPMIEN bit (I2CxCON<11>) during an I
2
C
master operation and set this bit while acting as an IPMI slave.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-PIC24FJ32MC102-I2C.pdf