Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2005-2011 Microchip Technology Inc. DS70157F-page 29
Section 2. Programmer’s Model
Programmers
Model
2
Register 2-3: SR: CPU STATUS Register (dsPIC33E Devices)
R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R -0 R/W-0
OA OB SA
(3)
SB
(3)
OAB SAB DA DC
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2
(1,2)
IPL1
(1,2)
IPL0
(1,2)
RA N OV Z C
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit C = Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation Status bit
1 = Accumulator A is saturated or has been saturated since this bit was last cleared
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation Status bit
1 = Accumulator B is saturated or has been saturated since this bit was last cleared
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulator A or B has overflowed
0 = Neither Accumulator A nor B has overflowed
bit 10 SAB: SA || SB Combined Accumulator Status bit
1 = Accumulator A or B is saturated or has been saturated since this bit was last cleared
0 = Neither Accumulator A nor B is saturated
bit 9 DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow
bit
1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data
of the result occurred
0 = No carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data
of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL3 = 1. User interrupts are disabled when IPL3 = 1.
2: The IPL<2:0> Status bits are read only when NSTDIS bit (INTCON1<15>) = 1. Refer to the family
reference manual of the specific device family to see the associated interrupt register.
3: A data write to SR can modify the SA or SB bits by either a data write to SA and SB or by clearing the SAB
bit. To avoid a possible SA/SB bit write race-condition, the SA and SB bits should not be modified using bit
operations.

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