Vault 7: Projects

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PIC24F Family Reference Manual
DS39712D-page 7-2 © 2011 Microchip Technology Inc.
7.1 INTRODUCTION
The Reset module combines all Reset sources and controls the device Master Reset signal,
SYSRST
. The following is a list of device Reset sources:
POR: Power-on Reset
MCLR: Pin Reset
SWR: RESET Instruction
WDTR: Watchdog Timer Reset
BOR: Brown-out Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Opcode/Uninitialized W Register Reset
Figure 7-1 displays a simplified block diagram of the Reset module. Any active source of Reset
will make the SYSRST
signal active. Many registers associated with the CPU and peripherals
are forced to a known “Reset state”. Most registers are unaffected by a Reset; their status is
unknown on Power-on Reset (POR) and unchanged by all other Resets.
All types of device Resets will set a corresponding status bit in the RCON register to indicate the
type of Reset (see Register 7-1). A POR will clear all bits, except for the BOR and POR bits
(RCON<1:0>) which are set. Users may set or clear any of the bits at any time during code
execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in
software will not cause a device Reset.
The RCON register also has other bits associated with the Watchdog Timer (WDT) and device
power-saving states. For more information on the function of these bits, refer to Section 7.13.2
“Using the RCON Status Bits”.
Figure 7-1: Reset System Block Diagram
Note: Refer to the specific peripheral or CPU section of this manual for register Reset
states.
MCLR
VDD
VDD Rise
Detect
POR
Sleep or Idle
Brown-out
Reset
RESET
Instruction
WDT
Module
Glitch Filter
BOR
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
Voltage Regulator Enable
Only in Devices with
On-Chip Regulator

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