Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

2007-2014 Microchip Technology Inc. DS70000195F-page 43
Figure 7-6: I
2
C™ Slave, 7-Bit Address, Transmission (AHEN = 1)
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6
SDAx
SCLx
SI2CxIF
RBF
ACKDT
SCLREL
ACK
R/W = 1
ACK
ACKTIM
TBF
1 2
3 4 5 6 7 8 9
1110
1
Detecting Start bit, enables address detection, interrupt is set if the SCEN bit is set.
2
User software clears the interrupt flag.
3 Slave receives the address byte with R/W = 1. Hardware clears the SCLREL to
suspend master clock. ACKTIM and interrupt flag are asserted.
4
User software clears the interrupt flag.
5
Software reads the I2CxRV register, that clears the RBF flag.
6 ACKDT is written with ACK.
7
User software sets SCLREL to release clock hold. Master clocks in the
Acknowledgment sequence. ACKTIM is cleared by hardware.
9
User software clears the interrupt flag.
10
User software loads the I2CxTRN register with response dat
indicates that the buffer is full.
11
After last bit, module clears TBF bit, indicating buffer is ava
12
At the end of ninth clock, if master sent NACK, no mo
Module does not suspend the clock.
13
Module recognizes Stop event.
8 Hardware clears SCLREL to suspend master clock if R/

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