Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2010 Microchip Technology Inc. Preliminary DS39735A-page 47-29
Section 47. Motor Control PWM
Motor Control
PWM
47
47.10 DUTY CYCLE REGISTER BUFFERING
The four PWM Duty Cycle registers, PxDC3:PxDC1, are buffered to allow glitchless updates of
the PWM outputs. For each generator, there is a PxDC3:PxDC1 register (buffer register) that is
accessible by the user application and a non-memory mapped Duty Cycle register that holds
the actual compare value. The PWM duty cycle is updated with the value in the PxDC3:PxDC1
register at specific times in the PWM period to avoid glitches in the PWM output signal.
When the PWM time base is operating in Free-Running or Single Event mode
(PTMOD<1:0> = 0x), the PWM duty cycle is updated whenever a match with the PxTPER
register occurs and PxTMR is reset to 0.
When the PWM time base is operating in Up/Down Counting mode (PTMOD<1:0> = 10), duty
cycles are updated when the value of the PxTMR register is zero and the PWM time base
begins to count upward. Figure 47-12 indicates the times when the duty cycle updates occur
for Up/Down Counting mode.
When the PWM time base is in Up/Down Counting mode with double updates
(PTMOD<1:0> = 11), duty cycles are updated when the value of the PxTMR register is zero
and when the value of the PxTMR register matches the value in the PxTPER register.
Figure 47-12 and Figure 47-13 indicate the times when the duty cycle updates occur for this
mode of the PWM time base.
Figure 47-12: Duty Cycle Update Times in Up/Down Counting Mode
Figure 47-13: Duty Cycle Update Times in Up/Down Counting Mode with
Double Updates
Note: Any write to the PxDC3:PxDC1 registers immediately updates the duty cycle when
the PWM time base is disabled (PTEN = 0). This allows a duty cycle change to take
effect before PWM signal generation is enabled.
PxTMR Value
PWM Output
Duty Cycle Value Loaded from PxDC3:PxDC1 Register, CPU Interrupted
New Value Written to PxDC3:PxDC1 Register
PxTMR Value
PWM Output
Duty Cycle Value Loaded from PxDC3:PxDC1 Register, CPU Interrupted
New Values Written to PxDC3:PxDC1 Register
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section47-Motor_Control_PWM.pdf