Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 14 2007-2014 Microchip Technology Inc.
Register 3-4: I2CxSTAT: I2Cx Status Register
R-0, HSC R-0, HSC R-0, HSC U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT TRSTAT ACKTIM
(1)
BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D/A
P S R/W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HS = Hardware Settable bit
bit 15 ACKSTAT: Acknowledge Status bit
1 = NACK received from slave
0 = ACK
received from slave
Hardware sets or clears at the end of slave or master Acknowledge.
bit 14 TRSTAT: Transmit Status bit (I
2
C™ Master mode transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware sets at the beginning of master transmission; hardware clears at the end of slave Acknowledge.
bit 13 ACKTIM: Acknowledge Time Status bit (valid in I
2
C Slave mode only)
(1)
1 = Indicates that the I
2
C bus is in an Acknowledge sequence; set on the falling edge of eighth SCLx clock
0 = Not an Acknowledge sequence, cleared on ninth rising edge of the SCLx clock
Hardware sets at the beginning of master transmission; hardware clears at the end of slave Acknowledge.
bit 12-11 Unimplemented: Read as0
bit 10 BCL: Bus Collision Detect bit (Master and Slave
modes)
1 = A bus collision has been detected during a master or slave operation
0 = No collision
Hardware sets at detection of a bus collision; clears when I
2
C module is disabled, I2CEN = 0.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware sets when address matches general call address; hardware clears at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware sets at match of second byte of matched 10-bit address; hardware clears at Stop detection.
bit 7 IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I
2
C module is busy
0 = No collision
Hardware sets at occurrence of a write to the I2CxTRN register while busy (cleared by software).
bit 6 I2COV: I2Cx Receive Overflow Flag bit
1 = A byte is received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware sets at attempt to transfer the I2CxRSR register to the I2CxRCV register (cleared by software).
Note 1: Refer to the specific device data sheet for availability of the ACKTIM bit.

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