Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
PIC24F Family Reference Manual
DS39699B-page 23-21 Advance Information © 2007 Microchip Technology Inc.
23.3.4.4 SPI MASTER MODE AND FRAME SLAVE MODE
In Master/Frame Slave mode, the module generates the clock signal but uses the slave module’s
frame synchronization signal for data transmission (Figure 23-12). It is enabled by setting the
MSTEN, FRMEN and the SPIFSD bits to ‘1’.
In this mode, the SSx
pin is an input and it is sampled on the sample edge of the SPIx clock.
When it is sampled in its active state, data will be transmitted on the subsequent transmit edge
of the SPIx clock. The interrupt flag, SPIxIF, is set when the transmission is complete. The user
must make sure that the correct data is loaded into the SPIxBUF for transmission before the
signal is received at the SSx
pin.
Figure 23-12: SPI Master, Frame Slave Connection Diagram
Figure 23-13: SPI Master, Frame Slave Timing (SPIFE = 0)
Figure 23-14: SPI Master, Frame Slave Timing (SPIFE = 1)
SDOx
SDIx
PIC24F
Serial Clock
SSx
SCKx
Frame Sync
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPI Master, Frame Slave)
SCKx
SDOx
(CKP = 0)
Bit 14 Bit 13 Bit 12
SDIx
Sample SSx
pin for Pulse
Receive Samples at SDIx
Bit 14
Bit 13
Bit 12
Write to SPIxBUF
SCKx
(CKP = 1)
SSx
(SPIFPOL=1)
SSx
(SPIFPOL=0)
Bit 15
Bit 15
SCKx
SDOx
(CKP = 0)
Bit 14 Bit 13 Bit 12
SDIx
Bit 14
Bit 13
Bit 12
SCKx
(CKP = 1)
Write to SPIxBUF
Pulse Generated by SSx,
Receive Samples at SDIx
SSx
(SPIFPOL=1)
SSx
(SPIFPOL=0)
Bit 15
Bit 15
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section23-Serial_Peripheral_Interface.pdf