Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
PIC24F Family Reference Manual
DS39735A-page 47-38 Preliminary © 2010 Microchip Technology Inc.
47.13.3.1 ENTRY INTO A FAULT CONDITION
When a Fault pin is enabled and driven low, the PWM pins are immediately driven to their
programmed Fault states regardless of the values in the PWM Duty Cycle (PxDCy) and
Override Control (PxOVDCON) registers. The Fault action has priority over all other PWM
control registers.
47.13.3.2 EXIT FROM A FAULT CONDITION
A Fault condition must be cleared by the external circuitry driving the Fault input pin high and
clearing the Fault interrupt flag (Latched mode only). After the Fault pin condition has been
cleared, the PWM module restores the PWM output signals on the next PWM period or
half-period boundary. For edge-aligned PWM generation, the PWM outputs are restored when
PxTMR = 0. For center-aligned PWM generation, the PWM outputs are restored when
PxTMR = 0 or PxTMR = PxTPER, whichever event occurs first.
An exception to these rules occurs when the PWM time base is disabled (PTEN = 0). If the
PWM time base is disabled, the PWM module restores the PWM output signals immediately
after the Fault condition has been cleared.
47.13.4 Fault Pin Priority
If both Fault input pins have been assigned to control a particular pair of PWM pins, the Fault
states programmed for the FLTxA
input pin will take priority over the FLTxB input pin.
One of two actions will take place when the Fault A condition has been cleared. If the FLTxB
input is still asserted, the PWM outputs will return to the states programmed in the Fault B
Control (PxFLTBCON) register on the next period or half-period boundary. If the FLTxB
input is
not asserted, the PWM outputs will return to normal operation on the next period or half-period
boundary.
47.13.5 Fault Pin Software Control
Each of the Fault pins can be controlled manually in software. Since each Fault input is shared
with a PORT I/O pin, the PORT pin can be configured as an output by clearing the
corresponding TRIS bit. When the PORT bit for the pin is cleared, the Fault input is activated.
Note: When the FLTxA pin is programmed for Latched mode, the PWM outputs will not
return to the Fault B states or normal operation until the Fault A interrupt flag has
been cleared and the FLTxA pin is deasserted.
Note: Caution should be exercised when controlling the Fault inputs in software. If the
TRIS bit for the Fault pin is cleared, the Fault input cannot be driven externally.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section47-Motor_Control_PWM.pdf