Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
DS70000195F-page 30 2007-2014 Microchip Technology Inc.
Figure 5-9: Master Message (Typical I
2
C™ Message: Read of Serial EEPROM)
1
Setting the SEN bit starts a Start event.
AKDT
ACKEN
SEN
SCLx
SDAx
SCLx
SDAx
I2CxTRN
TBF
I2CxRCV
RBF
MI2CxIF
ACKSTAT
1 2 3 4 5 6 7 8
A1 A0
9
A
PEN
RCEN
1 2 3 4 5 6 7 8
A11
A10
A9
A8
1 2 3 4 5 6 7 8 9
W1 1
RSEN
1 2 3 4 5 6 7 8 9
1 32
9
A
1 2 3 4 5 6 7
D3 D2 D1D7 D6 D5 D4AA
4 5 7
2
Writing the I2CxTRN register starts a master transmission. The data is the serial
3
Writing the I2CxTRN register starts a master transmission. The data is the first
4
5
Writing the I2CxTRN register starts a master transmission.
6
Setting the RCEN bit starts a master reception. On interrupt
7
9
Setting the ACKEN bit starts an Acknowledge event. ACKDT
Setting the PEN bit starts a master Stop event.
EEPROM device address byte, with the R/W
status bit clear, indicating a write.
byte of the EEPROM data address.
the serial EEPROM device address byte, but with R/W
status bi
the I2CxRCV register, which clears the RBF status bit.
0 0 A2 A7 A6 A5 A4 A2 A1 A0 A1 A0 R1 10 0 A20 0 0 0
6
Writing the I2CxTRN register starts a master transmission. The data is the second
byte of the EEPROM data address.
8
Setting the RSEN bit starts a Repeated Start event.
(Master)
(Master)
(Slave)
(Slave)
A3
MI2CxIF Interrupt Flag Cleared by User Software
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-PIC24FJ32MC102-I2C.pdf