Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2005-2011 Microchip Technology Inc. DS70157F-page 429
Section 5. Instruction Descriptions
Instruction
Descriptions
5
TBLRDL Table Read Low
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} TBLRDL{.B} [Ws], Wd
[Ws++], [Wd]
[Ws--], [Wd++]
[++Ws], [Wd--]
[--Ws], [++Wd]
[--Wd]
Operands: Ws [W0 ... W15]
Wd [W0 ... W15]
Operation: For byte operation:
If (LSB(Ws) = 1)
Program Mem [(TBLPAG),(Ws)] <15:8> Wd
Else
Program Mem [(TBLPAG),(Ws)] <7:0> Wd
For word operation:
Program Mem [(TBLPAG),(Ws)] <15:0> Wd
Status Affected: None
Encoding: 1011 1010 0Bqq qddd dppp ssss
Description: Read the contents of the least significant word of program memory and
store it to the destination register Wd. The target word address of program
memory is formed by concatenating the 8-bit Table Pointer register,
TBLPAG<7:0>, with the effective address specified by Ws. Indirect
addressing must be used for Ws, and either register direct or indirect
addressing may be used for Wd.
In Word mode, the lower 2 bytes of program memory are stored to the
destination register. In Byte mode, the source address depends on the
contents of Ws. If Ws is not word-aligned, the second byte of the program
memory word (PM<15:7>) is stored to the destination register. If Ws is
word-aligned, the first byte of the program memory word (PM<7:0>) is
stored to the destination register.
The ‘B’ bit selects byte or word operation (‘0’ for word mode, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.
Words: 1
Cycles: 2 (PIC24F, PIC24H, dsPIC30F, dsPIC33F)
5 (PIC24E, dsPIC33E)

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