Vault 7: Projects

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© 2005-2011 Microchip Technology Inc. DS70157F-page 91
Section 4. Instruction Set Details
Instruction Set
Details
4
4.18 EXTENDED-PRECISON ARITHMETIC USING MIXED-SIGN
MULTIPLICATIONS (dsPIC33E ONLY)
Many DSP algorithms utilize extended-precision arithmetic operations (operations with 32-bit or
64-bit operands and results) to enhance the resolution and accuracy of computations. These can
be implemented using 16-bit signed or unsigned multiplications; however, this would require
some additional processing and shifting of the data to obtain the correct results. To enable such
extended-precision algorithms to be computed faster, dsPIC33E devices support an optional
implicit mixed-sign multiplication mode, which is selected by setting US<1:0>
(CORCON<13:12>) = '10'.
In this mode, mixed-sign (unsigned x signed and signed x unsigned) multiplications can be
performed without the need to dynamically reconfigure the US<1:0> bits and shift data to account
for the difference in operand formats. Moreover, signed x signed and unsigned x unsigned
multiplications can also be performed without changing the multiplication mode. Each input
operand is implicitly treated as an unsigned number if the working register being used to specify
the operand is either W4 or W6. Similarly, an operand is treated as a signed number if the register
used is either W5 or W7. The DSP Engine selects the type of multiplication to be performed
based on the operand registers used, thereby eliminating the need for the user software to
modify the US<1:0> bits.
The execution time reductions provided by the implicit mixed-sign multiplication feature is
illustrated in the following code example, where the instruction cycle count for performing a 32-bit
multiplication is reduced from 7 cycles to 4 cycles when the mixed-sign multiplication mode is
enabled.
Example 4-25: 32-bit Signed Multiplication using Implicit Mixed-Sign Mode
Besides DSP instructions, MCU multiplication (MUL) instructions can also utilize Accumulator A
or Accumulator B as a result destination, which enables faster extended-precision arithmetic
even when not using DSP multiplication instructions such as MPY or MAC.
Case A - Mixed-Sign Multiplication Mode Not Enabled
MUL.SU W5, W6, W0; Word1 (signed) x Word2 (unsigned)
MUL.US W4, W7, W2; Word0 (unsigned) x Word3 (signed)
CLR B ; Clear Accumulator B
ADD W1, B
ADD W3, B
SFTAC B, #15 ; Shift right by 15 bits to align for Q31 format
MAC W5*W7, B; Word1 (signed) x Word 3 (signed)
Case B - Mixed-Sign Multiplication Mode Enabled
MPY W5*W6, B; Word1 (signed) x Word2 (unsigned)
MAC W4*W7, B; Word0 (unsigned) x Word3 (signed)
SFTAC B, #15 ; Shift right by 15 bits to align for Q31 format
MAC W5*W7, B; Word1 (signed) x Word 3 (signed)

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