Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2011 Microchip Technology Inc. DS39712D-page 7-11
Section 7. Reset
Reset
7
7.8 CONFIGURATION MISMATCH RESET
To maintain the integrity of the stored configuration values, all device Configuration bits are
implemented as a complementary set of register bits. For each bit, as the actual value of the
register is written as 1’, a complementary value, 0’, is stored in its corresponding background
register and vice versa. The bit pairs are compared every time, including Sleep mode. During this
comparison, if the Configuration bit values are not found opposite to each other, a Configuration
Mismatch event is generated which causes a device Reset.
If a device Reset occurs as a result of a Configuration Mismatch, the CM status bit (RCON<9>)
is set.
7.9 TRAP CONFLICT RESET (TCR)
A Trap Conflict Reset (TCR) occurs when a hard and a soft trap occur at the same time. The
TRAPR status bit (RCON<15>) is set on this event. Refer to Section 8. “Interrupts” in the
“PIC24F Family Reference Manualfor more information on traps.
7.10 ILLEGAL OPCODE RESET (IOPUWR)
A device Reset is generated if the device attempts to execute an illegal opcode value that was
fetched from program memory. If a device Reset occurs as a result of an illegal opcode value,
the IOPUWR status bit (RCON<14>) is set.
The Illegal Opcode Reset function can prevent the device from executing program memory
sections that are used to store constant data. To take advantage of the Illegal Opcode Reset, use
only the lower 16 bits of each program memory section to store the data values. The upper 8 bits
should be programmed with 3Fh, which is an illegal opcode value.
7.11 UNINITIALIZED W REGISTER RESET
The W register array (with the exception of W15) is cleared during all Resets and is considered
uninitialized until written to. An attempt to use an uninitialized register as an Address Pointer
causes a device Reset and sets the IOPUWR status bit (RCON<14>).
7.12 VBAT MODE
(1)
Entering VBAT mode is made possible for the device by connecting an external power source
(i.e., battery) to the VBAT pin. V
BAT mode is automatically triggered when the microcontrollers
main power supply on V
DD fails. VBAT mode can be entered from any of the other modes of oper-
ation (Run, Idle, Sleep, Deep Sleep). In addition, V
BAT mode is entered when VBAT is powered
from V
DD, if the VDDCORE power is lost but the VDD pin voltage is not. This maintains a few key
systems at an extremely low-power draw until V
DD is restored. In order to successfully enter VBAT
mode, the device must have at least one BOR monitor active.
After running in V
BAT mode, the device automatically wakes up when VDD is restored to the
device. Wake-up occurs with a POR, after which the device starts executing code from the Reset
vector. All SFRs, except the Deep Sleep semaphores, are reset to their POR values. If the RTCC
was not configured to run during V
BAT mode, it will be reset upon exit from VBAT mode. Wake-up
timing is similar to that for a normal POR.

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