Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
PIC24F Family Reference Manual
DS39707A-page 8-6 Advance Information © 2006 Microchip Technology Inc.
8.2.2.1 TRAP PRIORITY AND HARD TRAP CONFLICTS
If a higher priority trap occurs while any lower priority trap is in progress, processing of the lower
priority trap will be suspended and the higher priority trap will be Acknowledged and processed.
The lower priority trap will remain pending until processing of the higher priority trap completes.
Each hard trap that occurs must be Acknowledged before code execution of any type may
continue. If a lower priority hard trap occurs while a higher priority trap is pending, Acknowledged,
or is being processed, a hard trap conflict will occur. The conflict occurs because the lower
priority trap cannot be Acknowledged until processing for the higher priority trap completes.
The device is automatically reset in a hard trap conflict condition. The TRAPR status bit
(RCON<15>) is set when the Reset occurs, so that the condition may be detected in software.
8.2.2.2 OSCILLATOR FAILURE TRAP (HARD TRAP, LEVEL 14)
An oscillator failure trap event will be generated if the Fail-Safe Clock Monitor (FSCM) is enabled
and has detected a loss of the system clock source.
An oscillator failure trap event can be detected in software by polling the OSCFAIL status bit
(INTCON1<1>) or the CF status bit (OSCCON<3>). To avoid re-entering the Trap Service
Routine, the OSCFAIL status flag must be cleared in software prior to returning from the trap with
a RETFIE instruction.
Refer to Section 6. “Oscillator” and Section 32. “Device Configuration” for more information
about the FSCM.
8.2.2.3 ADDRESS ERROR TRAP (HARD TRAP, LEVEL 13)
The following paragraphs describe operating scenarios that would cause an address error trap
to be generated:
1. A misaligned data word fetch is attempted. This condition occurs when an instruction
performs a word access with the LSb of the effective address set to ‘1’. The PIC24F CPU
requires all word accesses to be aligned to an even address boundary.
2. A bit manipulation instruction using the Indirect Addressing mode with the LSb of the
effective address set to ‘1’.
3. A data fetch from unimplemented data address space is attempted.
4. Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where
literal is an unimplemented program memory address.
5. Executing instructions after modifying the PC to point to unimplemented program memory
addresses. The PC may be modified by loading a value into the stack and executing a
RETURN instruction.
Data space writes will be inhibited whenever an address error trap occurs, so that data is not
destroyed.
An address error can be detected in software by polling the ADDRERR status bit (INTCON1<3>).
To avoid re-entering the Trap Service Routine, the ADDRERR status flag must be cleared in
software prior to returning from the trap with a RETFIE instruction.
8.2.3 Disable Interrupts Instruction
The DISI (disable interrupts) instruction has the ability to disable interrupts for up to
16384 instruction cycles. This instruction is useful when time critical code segments must be
executed.
The DISI instruction only disables interrupts with priority levels 1-6. Priority level 7 interrupts and
all trap events still have the ability to interrupt the CPU when the DISI instruction is active.
The DISI instruction works in conjunction with the DISICNT register. When the DISICNT register
is non-zero, priority level 1-6 interrupts are disabled. The DISICNT register is decremented on
each subsequent instruction cycle. When the DISICNT register counts down to ‘0’, priority
level 1-6 interrupts will be re-enabled. The value specified in the DISI instruction includes all
cycles due to PSV accesses, instruction stalls, etc.
The DISICNT register is readable and writable. The user can terminate the effect of a previous
DISI instruction early by clearing the DISICNT register. The amount of time that interrupts are
disabled can also be increased by writing to or adding to DISICNT.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section8-Interrupts.pdf