Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2010 Microchip Technology Inc. Preliminary DS39741A-page 48-11
Section 48. Comparator with Blanking
Comparator with
Blanking
48
bit 2 ABNEN: AND Gate A1 B Input Inverted Enable bit
1 = Inverted MBI is connected to AND gate
0 = Inverted MBI is not connected to AND gate
bit 1 AAEN: AND Gate A1 A Input Enable bit
1 = MAI is connected to AND gate
0 = MAI is not connected to AND gate
bit 0 AANEN: AND Gate A1 A Input Inverted Enable bit
1 = Inverted MAI is connected to AND gate
0 = Inverted MAI is not connected to AND gate
Register 48-4: CMxMSKCON: Comparator Mask Gating Control Register (Continued)

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