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© 2010 Microchip Technology Inc. Preliminary DS39735A-page 47-9
Section 47. Motor Control PWM
Motor Control
PWM
47
Register 47-6: PWMxCON2: PWM Control Register 2
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
IUE OSYNC UDIS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as 0
bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111 = 1:16 postscale
0001 = 1:2 postscale
0000 = 1:1 postscale
bit 7-3 Unimplemented: Read as 0
bit 2 IUE: Immediate Update Enable bit
1 = Updates to the active PxDC3:PxDC1 registers are immediate
0 = Updates to the active PxDC3:PxDC1 registers are synchronized to the PWM time base
bit 1 OSYNC: Output Override Synchronization bit
1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base
0 = Output overrides via the PxOVDCON register occur on the next T
CY boundary
bit 0 UDIS: PWM Update Disable bit
1 = Updates from duty cycle and period buffer registers are disabled
0 = Updates from duty cycle and period buffer registers are enabled
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section47-Motor_Control_PWM.pdf