Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39700C-page 6-2 © 2009 Microchip Technology Inc.
6.1 INTRODUCTION
This section describes the PIC24F oscillator system and its operation. The PIC24F oscillator
system has the following modules and features:
A total of four external and internal oscillator options as clock sources, providing up to
11 different clock modes
An on-chip PLL block to boost internal operating frequency on select internal and external
oscillator sources, or (in select devices only) to provide a precise clock source for special
peripheral features
Software-controllable switching between various clock sources
Software-controllable postscaler for selective clocking of CPU for system power savings
A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application
recovery or shutdown
A programmable reference clock generator to provide a clock source with a wide range of
frequencies for synchronizing external devices (select devices only)
A simplified diagram of the oscillator system is shown in Figure 6-1.
Figure 6-1: PIC24F General System Clock Diagram
PIC24F Family
Secondary Oscillator
SOSCEN
Enable
Oscillator
SOSCO
SOSCI
Clock Source Option
for Other Modules
OSCI
OSCO
Primary Oscillator
XT, HS, EC
Postscaler
CLKDIV<10:8>
WDT, PWRT
8 MHz
FRCDIV
31 kHz (nominal)
FRC
Oscillator
LPRC
Oscillator
SOSC
LPRC
Clock Control Logic
Fail-Safe
Clock
Monitor
FRC
(nominal)
PLL Block
(1)
XTPLL, HSPLL
ECPLL,FRCPLL
CPU
Peripherals
Postscaler
CLKDIV<14:12>
CLKO
Reference Clock Generator
(2)
REFO
REFOCON<15:8>
Note 1: PLL block features are device-dependent. See Section 6.6 “Phase Lock Loop (PLL) Branch” for specific details.
2: The reference clock generator is not available in all devices.

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