Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2006 Microchip Technology Inc. Advance Information DS39716A-page 33-7
Section 33. Programming and Diagnostics
Programm
i
ng
and Diagnostics
33
Figure 33-4: TAP State Transitions for Shifting in an Instruction
33.4.2 JTAG Registers
The JTAG module uses a number of registers of various sizes as part of its operation. In terms
of bit count, most of the JTAG registers are single-bit register cells, integrated into the I/O ports.
Regardless of their location within the module, none of the JTAG registers are located within the
device data memory space, and cannot be directly accessed by the user in normal operating
modes.
33.4.2.1 INSTRUCTION SHIFT REGISTER AND INSTRUCTION REGISTER
The Instruction Shift register is a 4-bit shift register used for selecting the actions to be performed
and/or what data registers to be accessed. Instructions are shifted in, Least Significant bit first,
and then decoded.
A list and description of implemented instructions is given in Section 33.4.4 “JTAG Instructions”.
33.4.2.2 DATA REGISTERS
Once an instruction is shifted in and updated into the Instruction Register, the TAP controller
places certain data registers between the TDI and TDO pins. Additional data values can then be
shifted into these data registers as needed.
The PIC24F device family supports three data registers:
BYPASS Register: A single-bit register which allows the boundary scan test data to pass
through the selected device to adjacent devices. The BYPASS register is placed between
the TDI and TDO pins when the BYPASS instruction is active.
Device ID Register: A 32-bit part identifier. It consists of an 11-bit manufacturer ID assigned
by the IEEE (29h for Microchip Technology), device part number and device revision
identifier. When the IDCODE instruction is active, the Device ID register is placed between
the TDI and TDO pins. The device data ID is then shifted out on to the TDO pin, on the next
32 falling edges of TCK, after the TAP controller is in the Shift-DR.
MCHP Command Shift Register: An 8-bit shift register that is placed between the TDI and
TDO pins when the MCHP_CMD instruction is active. This shift register is used to shift in
Microchip commands.
TCK
TMS
TDI
TDO
TAP
State
Instruction Data (LSB)
Shift_IR
Test_Logic
Reset
Run_Test
Idle
Exit_IR
Update_IR
Run_Test
Idle
1
2
3
Note 1: TDO pin is always in a high-impedance state, until the first falling edge of TCK, in either the Shift_IR or Shift_DR states.
2: TDO is no longer high-impedance; the initial state of the Instruction Register (IR) is shifted out on the falling edge of TCK.
3: TDO returns to high-impedance again on the first falling edge of TCK in the Exit_IR state.
Select_DR_Scan Capture_IR
Select_IR_Scan

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