Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 26 2007-2014 Microchip Technology Inc.
5.4 Acknowledge Generation
Setting the ACKEN bit (I2CxCON<4> or I2CxCONL<4>) enables the generation of a master
Acknowledge sequence.
Figure 5-5 illustrates an ACK
sequence and Figure 5-6 illustrates a NACK sequence. The ACKDT
bit (I2CxCON<5> or I2CxCONL<5>) specifies an ACK
or NACK sequence.
After two baud periods, the ACKEN bit is automatically cleared and the module generates the
MI2CxIF interrupt.
5.4.1 IWCOL STATUS FLAG
If the user software writes the I2CxTRN register when an Acknowledge sequence is in progress,
the IWCOL status bit (I2CxSTAT<7>) is set and the contents of the buffer are unchanged (the
write does not occur).
Figure 5-5: Master Acknowledge (ACK
) Timing Diagram
Figure 5-6: Master Not Acknowledge (NACK) Timing Diagram
Note: The lower 5 bits of the I2CxCON or I2CxCONL register must be 0(master logic
inactive) before attempting to set the ACKEN bit.
Note: Because queuing of events is not allowed, writing to the lower 5 bits of the I2CxCON
or I2CxCONL register is disabled until the Acknowledge condition is complete.
SCLx (Master)
SDAx (Master)
ACKEN
MI2CxIF Interrupt
TBRG
1 2 3
Writing ACKEN = 1 initiates a master Acknowledge event.
1
TBRG
Writing ACKDT = 0 specifies sending an ACK.
When SCLx is detected low, the module drives SDAx low.
2
The BRG times out. Module releases SCLx. BRG restarts.
3
BRG times out.
4
I
2
C™ Bus State
(A) (Q)
(Q)
4
BRG starts. SCLx remains low.
Module drives SCLx low, then releases SDAx.
Module clears ACKEN. Master generates the interrupt.
(Q)
ACKDT = 0
SCLx (Master)
SDAx (Master)
ACKEN
MI2CxIF Interrupt
TBRG
1 2 3
Writing ACKEN = 1 initiates a master Acknowledge event.
1
T
BRG
Writing ACKDT = 1 specifies sending a NACK.
When SCLx is detected low, the module releases SDAx.
2
The BRG times out. Module releases SCLx. BRG restarts.
3
The BRG times out.
4
I
2
C™ Bus State
(A) (I)
(Q)
4
BRG starts.
Module drives SCLx low, then releases SDAx.
Module clears ACKEN. Master generates the interrupt.
ACKDT = 1
(Q)

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