Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2014 Microchip Technology Inc. DS70005185A-page 7
Serial Peripheral Interface (SPI) Module
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB buffer is full
0 = Transmit has started, SPIxTXB buffer is empty
Standard Buffer mode:
Automatically set in hardware when the core writes to the SPIxBUF location, loading the SPIxTXB.
Automatically cleared in hardware when the SPIx module transfers data from the SPIxTXB to SPIxSR.
Enhanced Buffer mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Receive is incomplete, SPIxRXB is empty
Standard Buffer mode:
Automatically set in the hardware when the SPIx transfers data from the SPIxSR to SPIxRXB. Automatically
cleared in the hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer mode:
Automatically set in hardware when the SPIx transfers data from the SPIxSR to the buffer, filling the last
unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer
from SPIxSR.
Register 2-1: SPIxSTAT: SPIx Status and Control Register (Continued)
Note 1: These bits are not implemented on the dsPIC33/PIC24 devices as they do not support the
Enhanced Buffer mode.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf