Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2009-2013 Microchip Technology Inc. DS70000582E-page 15
UART
5.0 UART TRANSMITTER
The transmitter block diagram of the UART module is illustrated in Figure 5-1. The important part
of the transmitter is the UARTx Transmit Shift Register (UxTSR). The Shift register obtains its
data from the transmit FIFO buffer, UxTXREG. The UxTXREG register is loaded with data in soft-
ware. The UxTSR register is not loaded until the Stop bit has been transmitted from the previous
load. As soon as the Stop bit is transmitted, the UxTSR is loaded with new data from the
UxTXREG register (if available).
Figure 5-1: UARTx Transmitter Block Diagram
The transmission is enabled by setting the UTXEN enable bit (UxSTA<10>). The actual trans-
mission will not occur until the UxTXREG register has been loaded with data and the Baud Rate
Generator (UxBRG) has produced a shift clock (Figure 5-1). Normally, when the first transmis-
sion is started, the UxTSR register is empty, so a transfer to the UxTXREG register will result in
an immediate transfer to UxTSR. Clearing the UTXEN bit during a transmission will cause the
transmission to be aborted and will reset the transmitter. As a result, the UxTX pin will revert to
a high-impedance state.
To select 9-bit transmission, the PDSEL<1:0> bits (UxMODE<2:1>) should be set to 11 and the
ninth bit should be written to the UTX8 bit (UxTXREG<8>). A word write should be performed to
UxTXREG, so that all nine bits are written at the same time.
Note: The UxTSR register is not mapped in data memory, so it is not available to the user
application.
Word Write-Only
Word or
UTX8 UxTXREG Low Byte
Load UxTSR
Transmit Control
Control UxTSR
Control Buffer
Generate Flags
Generate Interrupt
UxTXIF
Data
(Start)
(Stop)
Parity
Parity
Generator
Transmit Shift Register (UxTSR)
Control
Signals
16x Baud Clock
from Baud Rate
Generator
Internal Data Bus
UTXBRK
Note: x denotes the UART number.
UxTX
UxMODE
UxSTA
16
Byte Write
Transmit FIFO
15 9 8 7 0
UxCTS
UTXINV
16 Divider
Note: There is no parity in case of a 9-bit data transmission.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-PIC24FJ32MC102-UART.pdf