Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2005-2011 Microchip Technology Inc. DS70157F-page 87
Section 4. Instruction Set Details
Instruction Set
Details
4
Example 4-21: MAC Accumulator WB Syntax
Putting it all together, an MSC instruction which performs two prefetches and a write back is
shown in Example 4-22.
Example 4-22: MSC Instruction with Two Prefetches and Accumulator Write Back
ACCB W13
0 ACCA
; CLR with direct WB of ACCB
CLR A, W13
ACCB [W13]+=2
ACCA=ACCA+W4*W5
; MAC with indirect WB of ACCB
MAC W4*W5, A [W13]+=2
Y([W10]+=2) W4
ACCB=ACCB+W4*W5
ACCA W13
; MAC with Y prefetch, direct WB of ACCA
MAC W4*W5, B, [W10]+=2, W4, W13
ACCB=ACCB-W6*W7
X([W8]+=2)W6
Y([W10]-=6)W7
ACCA[W13]+=2
; MSC with X/Y prefetch, indirect WB of ACCA
MSC W6*W7, B, [W8]+=2, W6, [W10]-=6, W7 [W13]+=2

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