Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 122 © 2005-2011 Microchip Technology Inc.
ASR
Arithmetic Shift Right by Wns
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} ASR Wb, Wns, Wnd
Operands:
Wb [W0 ... W15]
Wns [W0 ...W15]
Wnd [W0 ... W15]
Operation:
Wns<3:0> Shift_Val
Wb<15> Wnd<15:15-Shift_Val + 1>
Wb<15:Shift_Val> Wnd<15-Shift_Val:0>
Status Affected:
N, Z
Encoding: 1101 1110 1www wddd d000 ssss
Description: Arithmetic shift right the contents of the source register Wb by the 4 Least
Significant bits of Wns (up to 15 positions) and store the result in the
destination register Wnd. After the shift is performed, the result is
sign-extended. Direct addressing must be used for Wb, Wns and Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the destination register.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: If Wns is greater than 15, Wnd = 0x0 if Wb is positive, and
Wnd = 0xFFFF if Wb is negative.
Words: 1
Cycles: 1
Example 1:
ASR W0, W5, W6 ; ASR W0 by W5 and store to W6
Before
Instruction
After
Instruction
W0 80FF W0 80FF
W5 0004 W5 0004
W6 2633 W6 F80F
SR 0000 SR 0000
Example 2:
ASR W0, W5, W6 ; ASR W0 by W5 and store to W6
Before
Instruction
After
Instruction
W0 6688 W0 6688
W5 000A W5 000A
W6 FF00 W6 0019
SR 0000 SR 0000
Example 3:
ASR W11, W12, W13 ; ASR W11 by W12 and store to W13
Before
Instruction
After
Instruction
W11 8765 W11 8765
W12 88E4 W12 88E4
W13 A5A5 W13 F876
SR 0000 SR 0008 (N = 1)

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh