Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2011 Microchip Technology Inc. DS39712D-page 7-15
Section 7. Reset
Reset
7
7.14 DEVICE RESET TO CODE EXECUTION START TIME
The delay between the end of a Reset event and when the device actually begins to execute
code is determined by two main factors: the type of Reset and the system clock source coming
out of the Reset. The code execution start time for various types of device Resets is summarized
in Table 7-5. Individual delays are characterized in Section 7.16 “Electrical Specifications”.
For POR, the system Reset signal, SYSRST
, is released after the POR delay time (TPOR) and
the T
STARTUP delay time expires. For BOR, SYSRST is released after the TSTARTUP delay time
expires. For all other Resets, the system Reset signal, SYSRST
, is released immediately after
the Reset condition is removed. For all Resets, the T
RST delay starts after the SYSRST is
released. The system clock starts at the expiration of T
RST; code execution starts after the clock
source is stable.
The time that the device actually begins to execute code also depends on the system oscillator
delays, which include the Oscillator Start-up Timer delay (T
OST) and the PLL lock time (TLOCK).
The PLL lock is additive to (i.e., occurs after) the OST.
Table 7-5: Reset Delay Times for Various Device Resets
Reset Type Clock Source SYSRST
Delay
System Clock
Delay
Notes
POR
(6)
EC TPOR + TRST + TSTARTUP — 1, 2, 3
FRC, FRCDIV TPOR + TRST + TSTARTUP TFRC 1, 2, 3, 4, 7
LPRC T
POR + TRST + TSTARTUP TLPRC 1, 2, 3, 4
ECPLL TPOR + TRST + TSTARTUP TLOCK 1, 2, 3, 5
FRCPLL TPOR + TRST + TSTARTUP TFRC + TLOCK 1, 2, 3, 4, 5
XT, HS, SOSC T
POR + TRST + TSTARTUP TOST 1, 2, 3, 6
XTPLL, HSPLL TPOR + TRST + TSTARTUP TOST + TLOCK 1, 2, 3, 5, 6
BOR EC TRST + TSTARTUP — 2, 3
FRC, FRCDIV T
RST + TSTARTUP TFRC 2, 3, 4, 7
LPRC TRST + TSTARTUP TLPRC 2, 3, 4
ECPLL TRST + TSTARTUP TLOCK 2, 3, 5
FRCPLL T
RST + TSTARTUP TFRC + TLOCK 2, 3, 4, 5
XT, HS, SOSC TRST + TSTARTUP TOST + TLOCK 2, 3, 6
XTPLL, HSPLL TRST + TSTARTUP TFRC + TLOCK 2, 3, 4, 5
All Others Any Clock T
RST — 2
Note 1: T
POR = Power-on Reset delay.
2: TRST = Internal State Reset time.
3: T
STARTUP = TVREG if the regulator is enabled or TPWRT (64 ms nominal) if the regulator is disabled.
4: T
FRC and TLPRC = RC oscillator start-up times.
5: TLOCK = PLL lock time.
6: T
OST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
7: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC,
and in such cases, FRC start-up time is valid.
Note: For nominal operating frequency and timing specifications, see Section 7.16 “Electrical Specifica-
tions”.For a particular device’s specifications, refer to the “Electrical Specifications” section of the
appropriate data sheet.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual_Section7-Reset.pdf