Vault 7: Projects
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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 168 © 2005-2011 Microchip Technology Inc.
BTST
Bit Test f
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BTST{.B} f, #bit4
Operands: f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation
Operation: (f)<
bit4> → Z
Status Affected: Z
Encoding: 1010 1011 bbbf ffff ffff fffb
Description: Bit ‘bit4’ in file register ‘f’ is tested and the complement of the tested bit is
stored to the Z flag in the STATUS register. The contents of the file
register are not changed. For the bit4 operand, bit numbering begins with
the Least Significant bit (bit 0) and advances to the Most Significant bit
(bit 7 for byte operation, bit 15 for word operation).
The ‘b’ bits select value bit4, the bit position to be tested.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
BTST.B 0x1201, #0x3 ; Set Z = complement of
; bit 3 in 0x1201
Before
Instruction
After
Instruction
Data 1200 F7FF Data 1200 F7FF
SR 0000 SR 0002 (Z = 1)
Example 2:
BTST 0x1302, #0x7 ; Set Z = complement of
; bit 7 in 0x1302
Before
Instruction
After
Instruction
Data 1302 F7FF Data 1302 F7FF
SR 0002 (Z = 1) SR 0000
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf