Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2009 Microchip Technology Inc. DS39700C-page 6-19
Section 6. Oscillator
Oscillator
6
6.6.2 96 MHz PLL Block
For PIC24F devices with USB features (such as the PIC24FJ256GB110 family) and graphics
controller features (such as the PIC24FJ256DA210 family), a 96 MHz PLL block is implemented
to generate the stable 48 MHz clock required for full-speed USB operation, a programmable
clock output for the graphics controller module and the system clock from the same oscillator
source. The 96 MHz PLL block is shown in Figure 6-8.
The 96 MHz PLL block requires a 4 MHz input signal; it uses this to generate a 96 MHz signal
from a fixed, 24 x PLL. This is, in turn, divided into three branches. The first branch generates
the USB clock, the second branch generates the system clock and the third branch generates
the graphics clock. The 96 MHz PLL block can be enabled and disabled using the PLL96MHZ
Configuration bit (Configuration Word 2 <11> in most devices) or through the PLLEN
(CLKDIV<5>) control bit when the PLL96MHZ Configuration bit is not set. Note that the
PLL96MHZ Configuration bit and the PLLEN register bit are available only for PIC24F devices
with USB and graphics controller modules.
The 96 MHz PLL prescaler does not automatically sense the incoming oscillator frequency. The
user must manually configure the PLL divider to generate the required 4 MHz output, using the
PLLDIV<2:0> Configuration bits (Configuration Word 2 <14:12> in most devices).
Figure 6-8: 96 MHz PLL Block
96 MHz
PLL
PLL Prescaler
PLLDIV<2:0>
Input from
POSC
Input from
FRC
÷12
÷ 8
÷ 6
÷ 5
÷ 4
÷ 3
÷ 2
÷ 1
111
110
101
100
011
010
001
000
FNOSC<2:0>
÷ 2
÷ 3
48 MHz Clock
for USB Module
Postsclaer
÷64
÷63
...
÷17.50
÷17.00
...
÷1.25
÷1
127
126
...
65
64
...
1
0
GCLKDIV<6:0>
Clock Output for
Display Interface
(DISPCLK)
÷ 2
0
1
Clock Output
for Graphics
Controller
Module (G1CLK)
G1CLKSEL
Graphics Clock
Option 2
Postsclaer
CPDIV<1:0>
÷ 8
÷ 4
÷ 2
÷ 1
11
10
01
00
PLL Output for
System Clock
4 MHz or
8 MHz
96 MHz Branch
96 MHz PLL
USB Clock
...
Graphics Clock
System Clock
4 MHz Branch
Graphics Clock
Option 1
48 MHz Branch
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section6-Oscillator.pdf