Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2006 Microchip Technology Inc. Advance Information DS39703A-page 2-3
Section 2. CPU
CPU
2
Figure 2-1: PIC24F CPU Core Block Diagram
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
MCLR
Timing
Generation
16
PCH PCL
16
Program Counter
16-Bit ALU
23
23
24
23
Data Bus
IR
PCU
16
16 x 16
W Reg Array
ROM Latch
16
EA MUX
RAGU
WAGU
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Data
RAM
Address
Latch
Control Signals
to Various Blocks
Address Latch
Program Memory
Data Latch
I/O Ports
16
16
Address Bus
16
Literal Data
Peripherals
Multiplier
and Divide
Support
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section2-CPU.pdf