Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

DS70000195F-page 40 2007-2014 Microchip Technology Inc.
Figure 7-3: I
2
C™ Slave, 7-Bit Address, Reception (STREN = 0, AHEN = 1, DHEN = 1)
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDAx
SCLx
RBF
SCLREL
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8
ACKDT
ACKTIM
SI2CxIF
1
2
3 4 5 6 7 8
9
14
13
12
1110
1
Detecting Start bit enable address detection, interrupt flag is set if SCEN is set.
2
3
4
5
9
11
12
13
6
7
User software clears the interrupt flag.
Slave receives the address byte with R/W =
0
. Hardware clears the SCLREL.
Interrupt flag is asserted. ACKTIM is asserted. I2CxRCV is loaded with
User software clears the interrupt flag.
User software reads I2CxRCV, that clears the RBF flag.
ACKDT is written with ACK
by user software.
User software sets SCLREL bit to release clock, ACKTIM is cleared by hardware.
8
Interrupt flag is set (not set if NACK is received).
User software clears the interrupt flag.
If DHEN =
1
, hardware clears SCLREL bit. I2CxRCV is
ACKTIM is asserted at the end of 8
th
falling edge of SCLx
User software reads I2CxRCV; clears the RBF flag.
User software releases the SCLREL, ACKTIM is cleared by hardware.
Interrupt flag is set.
14
User software clears the interrupt flag.
15
NACK.
I2CxRSR and RBF is asserted.
16
Slave recognizes the Stop event.
ACK
10

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh