Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24FJ64GA004 FAMILY
DS39881E-page 142 2010-2013 Microchip Technology Inc.
FIGURE 15-1: SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
Internal Data Bus
SDIx
SDOx
SSx/FSYNCx
SCKx
SPIxSR
bit 0
Shift Control
Edge
Select
F
CY
Primary
1:1/4/16/64
Enable
Prescaler
Sync
SPIxBUF
Control
TransferTransfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Secondary
Prescaler
1:1 to 1:8
Clock
Control

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh