Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2009-2013 Microchip Technology Inc. DS70000582E-page 41
UART
Figure 14-2: Data Reception Using the LIN/J2602 Protocol
BRG
UxRX
bit 0
bit 1
Start
XXXXh 0000h
Edge 1
bit 2
bit 3
Edge 2
bit 4
bit 5
Edge 3
bit 6
bit 7
Edge 4
Stop bit
Edge 5
001Ch
Identifier, Data
and Checksum
Delimiter
Sync Byte
1 6
1. The user application first sets the WAKE bit and then the ABAUD bit.
2. An RX interrupt is generated because the device wakes up on the reception of the Break character.
3. The FERR bit is set.
4. The WAKE bit is cleared.
5. The auto-baud feature detects the first rising edge of the Sync byte.
6. The fifth rising edge of the Sync byte is detected. The ABAUD bit is cleared and the BRG counter is loaded with the
baud rate of the received data.
Auto-Cleared
WAKE bit
ABAUD bit
UxRXIF
52 3 4
Auto-Cleared
Counter
Break Character
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-PIC24FJ32MC102-UART.pdf