Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2010 Microchip Technology Inc. Preliminary DS39741A-page 48-3
Section 48. Comparator with Blanking
Comparator with
Blanking
48
Figure 48-1: Input Selection Logic Block Diagram
Figure 48-2: Digital Filter Interconnect Block Diagram
Comparator Voltage
C3
C1
Blanking
Function
Digital
Filter
C2
Reference
(Figure 48-7)
CVREF
(Figure 48-4)
(Figure 48-2)
+
V
IN-
V
IN+
+
V
IN-
V
IN+
+
V
IN-
V
IN+
BGSEL<1:0>
AVDD AVSS
AVDD 1.2VAVSS
MUX
C1INB
C1INC
C1IND
MUX
C1INA
INTREF
MUX
C2INB
C2INC
C2IND
MUX
C2INA
INTREF
CV
REFIN
MUX
C3INB
C3INC
C3IND
MUX
C3INA
INTREF
CV
REFIN
CVREFIN
C1OUT
CPOL
Interrupt
Logic
EVPOL<1:0>
COE
COUT
Blanking
Function
Digital
Filter
(Figure 48-4)
(Figure 48-2)
C2OUT
CPOL
Interrupt
Logic
EVPOL<1:0>
COE
COUT
Blanking
Function
Digital
Filter
(Figure 48-4)
(Figure 48-2)
C3OUT
CPOL
Interrupt
Logic
EVPOL<1:0>
COE
COUT
CXOUT
CFLTREN
Digital Filter
Timer2 match
F
CY
CFSEL<2:0>
÷CFDIV
From Blanking Logic
PWM Special Event Trigger

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