Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2009 Microchip Technology Inc. DS39700C-page 6-21
Section 6. Oscillator
Oscillator
6
6.6.2.3 GRAPHICS CLOCK GENERATION
For PIC24F devices with graphics controller features, two stable clock signals are generated.
The first clock is for the graphics controller module logic and the second clock is for the display
module interface logic that generates the signals for the display glass. Figure 6-8 shows this logic
in the graphics clock subblock. Both clock signals are generated from either the graphics clock
option 1 (96 MHz branch) or the graphics clock option 2 (48 MHz branch). Selection is set in the
multiplexer using the G1CLKSEL (CLKDIV<4>) control bit. The graphics controller module logic
directly uses the output of that multiplexer, while the display module interface clock is further con-
ditioned through a postscaler to generate 128 possible frequencies. The final clock output signal
is selected through a multiplexer using the GCLKDIV<6:0> (CLKDIV2<15:9> control bits. The
128 selections vary in increments of 0.25, 0.5 and 1. Refer to Table 6-5 for details. Note that for
applications that use the graphics controller module, the 96 MHz PLL must be enabled.
6.6.3 Considerations for Using the PLL Block
All PLL blocks use the LOCK bit (OSCCON<5>) as a read-only status bit to indicate the lock
status of the PLL. It is automatically set after the typical time delay for the PLL to achieve lock,
designated as T
LOCK. It is cleared at a POR and on clock switches when the PLL is selected as
a destination clock source. It remains clear when any clock source not using the PLL is selected.
If the PLL does not stabilize properly during start-up, LOCK may not reflect the actual status of
the PLL lock, nor does it detect when the PLL loses lock during normal operation. Refer to the
”Electrical Characteristics” section in the specific device data sheet for further information on
the PLL lock interval.
Using any PLL block with the FRC Oscillator provides a stable system clock for microcontroller
operations. In specific devices or families, this combination may not meet the frequency accuracy
requirements for use in synchronous communications.
USB operation is only possible with FRC
Oscillators that are implemented w
ith ±1/4% frequency accuracy. Serial communications using
UART is only possible when FRC Oscillators are implemented with ±2% frequency accuracy.
Refer to the “Electrical Characteristics” section of the particular device data sheet for specific
information.
If an application is being migrated between PIC24F platforms with different PLL blocks (e.g., from
a GA0 family device to a GB1 family device), the differences in PLL and clock options may
require the reconfiguration of peripherals that use the system clock. This is particularly true with
serial communications peripherals, such as the UARTs.
Table 6-5: Display Module Clock Frequency Division
GCLKDIV<6:0> Frequency Divisor
Display Module Clock
Frequency
96 MHz Input (48 MHz Input)
0000000 1 96 MHz (48 MHz)
0000001 1.25 (start incrementing by 0.25) 76.80 MHz (38.4 MHz)
0000010 1.5 64 MHz (32 MHz)
0111111 16.75 5.73 MHz (2.86 MHz)
1000000 17 5.65 MHz (2.82 MHz)
1000001 17.5 (start incrementing by 0.5) 5.49 MHz (2.74 MHz)
1000010 18 5.33 MHz (2.66 MHz)
1011111 32.5 2.95 MHz (1.47 MHz)
1100000 33 2.91 MHz (1.45 MHz)
1100001 34 (start incrementing by 1) 2.82 MHz (1.41 MHz)
1100010 35 2.74 MHz (1.37 MHz)
1111110 63 1.52 MHz (762 kHz)
1111111 64 1.50 MHz (750 kHz)

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