Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

2014 Microchip Technology Inc. DS70005185A-page 23
Serial Peripheral Interface (SPI) Module
3.4.1 ENHANCED BUFFER MASTER MODE
In Enhanced Buffer Master mode, the system clock is prescaled and then used as the serial
clock. The prescaling is based on the settings in the Primary Prescale bits (PPRE<1:0>) and
Secondary Prescale bits (SPRE<1:0>) in the SPIxCON1 register. The serial clock is output
through the SCKx pin to slave devices. Clock pulses are generated only when there is data to be
transmitted (see Section 4.0 “Master Mode Clock Frequency”). The CKP and CKE bits
determine on which edge of the clock data transmission occurs.
The CPU loads data to be transmitted into the transmit buffer by writing to the SPIxBUF register.
An SPIx transmission begins after the first buffer write. Up to eight data elements can be loaded.
The number of pending transfers is indicated by the SPIx Buffer Element Count bits
(SPIBEC<2:0>) in the SPIx Status and Control (SPIxSTAT<10:8>) register.
In Master mode, the buffer element count reflects the number of transfers pending in the transmit
buffer. In Slave mode, the buffer element count reflects the number of unread receptions in the
receive buffer. If the Shift register is empty, the first write will immediately load the Shift register,
leaving eight transmit buffer locations available.
After completion of an SPIx transfer, the receive buffer location is updated with the received data.
The CPU accesses the received data by reading the SPIxBUF register. After each CPU read, the
SPIxBUF points to the next buffer location. The SPIx transfers continue until all the pending data
transfers have completed.
The SPIx module operation in Enhanced Buffer Master mode is as described:
1. After the module is set up for Master mode of operation and is enabled, data to be transmit-
ted is written to the SPIxBUF register and is loaded into the next available transmit buffer
location. The SPITBF bit (SPIxSTAT<1>) is set after eight pending transfers are loaded.
2. The contents of the current buffer location are moved to the SPIx Shift register, SPIxSR.
The SPITBF bit is cleared by the module if a buffer location is available for a CPU write.
3. A series of 8/16 clock pulses shift out 8/16 bits of transmit data from the SPIxSR register
to the SDOx pin, and simultaneously, shift in the data at the SDIx pin into the SPIxSR
register.
4. When the transfer is complete, the following occurs:
When the ongoing transmit and receive operation is complete, the contents of the
SPIxSR register are moved into the next available location in the receive buffer.
If the last unread location is written by the SPIx module, the SPIRBF bit
(SPIxSTAT<0>) is set by the module, indicating that all buffer locations are full. The
SPIx interrupts can be enabled by selecting an Interrupt mode with the SISEL<2:0>
bits (SPIxSTAT<4:2>) and by setting the SPIx Interrupt Enable bit (SPIxIE). The
SPIxIF flag is not cleared automatically by the hardware.
After the SPIxBUF register is read by the user application, the hardware clears the
SPIRBF bit and the SPIxBUF register increments to the next unread receive buffer
location. If the SPIxBUF register reads beyond the last unread location, it will not
increment the buffer location. The SRXMPT bit (SPIxSTAT<5>) shows the status of the
RX FIFO. This bit is set if the RX FIFO is empty.
5. If the SPIRBF bit is set (receive buffer is full) when the SPIx module needs to transfer data
from the SPIxSR register to the buffer, the module will set the SPIROV bit (SPIxSTAT<6>),
indicating an overflow condition and set the SPIxIF bit.
6. Data to be transmitted can be written to the SPIxBUF register by the user application at
any time as long as the SPITBF bit (SPIxSTAT<1>) is clear. Up to eight pending transfers
can be loaded into the buffer allowing continuous transmission. The SRMPT bit
(SPIxSTAT<7>) shows the status of the SPIxSR register. The SRMPT status bit is set
when the SPIxSR register is empty and ready to send or receive the data.

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