Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2010 Microchip Technology Inc. DS39724B-page 11-3
Section 11. CTMU
CTMU
11
Figure 11-1: CTMU Block Diagram
CTEDG1
CTEDG2
Current Source
Edge
Control
Logic
CTMUCON or CTMUCONx
(1)
Pulse
Generator
A/D Converter Comparator 2
Input
Timer1
OC1
Current
Control
ITRIM<5:0>
IRNG<1:0>
CTMUICON
CTMU
Control
Logic
EDGEN
EDGSEQEN
EDG1SELx
EDG1POL
EDG2SELx
EDG2POL
EDG1STAT
EDG2STAT
TGEN
IDISSEN
CTTRIG
A/D Trigger
CTPLS
Comparator 2 Output
Note 1: Refer to the specific device data sheet to determine which registers are available on your particular device.
EDG1MOD
EDG2MOD

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