Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 20 2009-2013 Microchip Technology Inc.
6.0 DATA BIT DETECTION
6.1 16X Clock Mode (BRGH = 0)
In 16x Clock mode, each bit of the received data is 16 clock pulses wide. To detect the value of
an incoming data bit, the bit is sampled at the 7th, 8th and 9th rising edges of the clock. These
rising edges are called Majority Detection edges. This mode is more robust than 4x Clock mode.
Figure 6-1: 16x Clock Mode with Majority Detection
6.2 4X Clock Mode (BRGH = 1)
In 4x Clock mode, each bit of the received data is four clock pulses wide. The 4x Clock mode
does not provide enough edges to support the Majority Detection method. Therefore, the
received data is sampled at the one-half bit width.
Figure 6-2: 4x Clock Mode without Majority Detection
Note: In 16x Clock mode, each bit is sampled at 7th, 8th and 9th rising edges of the clock.
Idle Start bit bit 0
MD2
MD3
MD1
Start Bit Detected
16x Clock
Bit Clock
Internal Bit Counter
(Received Data)
Start bit bit 0 bit 1
Sample Point
4x Clock
Bit Clock
Internal Bit Counter
RX
Note: In 4x Clock mode, the sampling occurs only at the one-half bit width.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Universal_Asynchronous_Receiver_Transmitter.pdf