Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 260 © 2005-2011 Microchip Technology Inc.
IOR
Inclusive OR f and WREG
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} IOR{.B} f {,WREG}
Operands: f [0 ... 8191]
Operation: (f).IOR.(WREG) destination designated by D
Status Affected: N, Z
Encoding:
1011 0111 0BDf ffff ffff ffff
Description: Compute the logical inclusive OR operation of the contents of the working
register WREG and the contents of the file register and place the result in
the destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG. If
WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
IOR.B 0x1000 ; IOR WREG to (0x1000) (Byte mode)
; (Byte mode)
Before
Instruction
After
Instruction
WREG 1234 WREG 1234
Data 1000 FF00 Data 1000 FF34
SR 0000 SR 0000
Example 2:
IOR 0x1000, WREG ; IOR (0x1000) to WREG
; (Word mode)
Before
Instruction
After
Instruction
WREG 1234 WREG 1FBF
Data 1000 0FAB Data 1000 0FAB
SR 0008 (N = 1) SR 0000

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