Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39707A-page 8-4 Advance Information © 2006 Microchip Technology Inc.
8.1.4 CPU Priority Status
The CPU can operate at one of sixteen priority levels, 0-15. An interrupt or trap source must have
a priority level greater than the current CPU priority in order to initiate an exception process.
Peripheral and external interrupt sources can be programmed for levels 0-7, while CPU priority
levels 8-15 are reserved for trap sources. A trap is a non-maskable interrupt source intended to
detect hardware and software problems (see Section 8.2 “Non-Maskable Traps”). The priority
level for each trap source is fixed and only one trap is assigned to a priority level. Note that an
interrupt source programmed to priority level 0 is effectively disabled, since it can never be
greater than the CPU priority.
The current CPU priority level is indicated by the following four status bits:
IPL<2:0> status bits located in SR<7:5>
IPL3 status bit located in CORCON<3>
The IPL<2:0> status bits are readable and writable, so the user may modify these bits to disable
all sources of interrupts below a given priority level. If IPL<2:0> = 111, for example, the CPU
would not be interrupted by any source with a programmed priority level of 0, 1, 2 or 3.
Trap events have higher priority (8-15) than any user interrupt source. When the IPL3 bit is set,
a trap event is in progress. The IPL3 bit can be cleared, but not set by the user. In some
applications, it may be desirable to clear the IPL3 bit when a trap has occurred and branch to an
instruction other than the instruction after the one that originally caused the trap to occur.
All user interrupt sources can be disabled by setting IPL<2:0> = 111.
8.1.5 Interrupt Priority
Each peripheral interrupt source can be assigned to one of seven priority levels. The
user-assignable interrupt priority control bits for each individual interrupt are located in the Least
Significant 3 bits of each nibble within the IPCn register(s). Bit 3 of each nibble is not used and
is read as 0’. These bits define the priority level assigned to a particular interrupt. The usable
priority levels start at level 1 as the lowest priority and level 7 as the highest priority. If the IPCn
bits associated with an interrupt source are all cleared, then the interrupt source is effectively
disabled.
Since more than one interrupt request source may be assigned to a specific priority level, a
means is provided to resolve priority conflicts within a given user-assigned level. Each source of
interrupt has a natural order priority based on its location in the IVT. The lower numbered interrupt
vectors have higher natural priority, while the higher numbered vectors have lower natural
priority. For example, Interrupt Vector 0 is of the highest natural priority and Interrupt Vector 117
is of the lowest natural priority. The overall priority level for any pending source of interrupt is
determined first by the user-assigned priority of that source in the IPCn register, then by the
natural order priority within the IVT.
Natural order priority is used only to resolve conflicts between simultaneous pending interrupts
with the same user-assigned priority level. Once the priority conflict is resolved and the exception
process begins, the CPU can only be interrupted by a source with higher user-assigned priority.
Interrupts with the same user-assigned priority, but a higher natural order priority, that become
pending after the exception process begins will remain pending until the current exception
process completes.
The ability for the user to assign each interrupt source to one of seven priority levels means that
the user can give an interrupt with a low natural order priority a very high overall priority level. For
example, the Interrupt Vector 0 may be assigned to priority level 1, thus giving it a very low
effective priority.
Note: The IPL<2:0> bits become read-only bits when interrupt nesting is disabled. See
Section 8.2.4.2 “Interrupt Nesting” for more information.
Note: At a device Reset, the IPCn registers are initialized such that all user interrupt
sources are assigned to priority level 4.
Note: This document explains the generic interrupt structure. Refer to the specific device
data sheet for the peripherals and sources of each interrupt.

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