Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39703A-page 2-12 Advance Information © 2006 Microchip Technology Inc.
Register 2-2: CORCON: Core Control Register
U-0 U-0 U-0 U-0 U-0 U-0 U -0 U -0
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0
IPL3
(1)
PSV
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0
bit 3 IPL3: CPU Interrupt Priority Level Status bit
(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
bit 1-0 Unimplemented: Read as ‘0
Note 1: User interrupts are disabled when IPL3 = 1.

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