Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39699B-page 23-19 Advance Information © 2007 Microchip Technology Inc.
23.3.4 Framed SPI Modes
The module supports a basic Framed SPI protocol while operating in either Master or Slave
modes. The module uses four control bits to configure framed SPI operation:
FRMEN (SPIxCON2<15>) enables the Framed SPI modes and causes the SSx pin to be
used as a frame synchronization pulse input or output pin. The state of SSEN
(SPIxCON1<7>) is ignored.
SPIFSD (SPIxCON2<14>) determines whether the SSx
pin is an input or an output
(i.e., whether the module receives or generates the frame synchronization pulse).
SPIFPOL (SPIxCON2<13>) selects the polarity of the frame synchronization pulse
(active-high or active-low) for a single SPIx data frame.
SPIFE (SPIxCON2<1>) selects the synchronization pulse to either coincide with, or
precede, the first serial clock pulse.
The SPIx module supports two Framed modes of operation. In Frame Master mode, the SPIx
module generates the frame synchronization pulse and provides this pulse to other devices at
the SSx
pin. In Frame Slave mode, the SPIx module uses a frame synchronization pulse
received at the SSx
pin.
The Framed SPI modes are supported in conjunction with the Unframed Master and Slave
modes. This makes four framed SPI configurations available to the user:
SPI Master mode and Frame Master mode
SPI Master mode and Frame Slave mode
SPI Slave mode and Frame Master mode
SPI Slave mode and Frame Slave mode
These modes determine whether or not the SPIx module generates the serial clock and the
frame synchronization pulse.
23.3.4.1 SCKx PIN IN FRAMED SPI MODES
When FRMEN = 1 and MSTEN = 1, the SCKx pin becomes an output and the SPIx clock at SCKx
becomes a free-running clock. When FRMEN = 1 and MSTEN = 0, the SCKx pin becomes an
input. The source clock provided to the SCKx pin is assumed to be a free-running clock.
The polarity of the clock is selected by the CKP (SPIxCON1<6>) bit. The CKE (SPIxCON1<8>)
bit is not used for the Framed SPI modes and should be programmed to ‘0 by the user software.
When CKP = 0, the frame sync pulse output and the SDOx data output change on the rising edge
of the clock pulses at the SCKx pin. Input data is sampled at the SDIx input pin on the falling edge
of the serial clock. When CKP = 1, the frame sync pulse output and the SDOx data output change
on the falling edge of the clock pulses at the SCKx pin. Input data is sampled at the SDIx input
pin on the rising edge of the serial clock.
23.3.4.2 SPIx BUFFERS IN FRAMED SPI MODES
When SPIFSD (SPIxCON2<14>) = 0, the SPIx module is in the Frame Master mode of operation.
In this mode, the frame sync pulse is initiated by the module when the user software writes the
transmit data to the SPIxBUF location (thus writing the SPIxTXB register with transmit data). At
the end of the frame sync pulse, the SPIxTXB is transferred to the SPIxSR and data
transmission/reception begins.
When SPIFSD = 1, the module is in Frame Slave mode. In this mode, the frame sync pulse is
generated by an external source. When the module samples the frame sync pulse, it will transfer
the contents of the SPIxTXB register to the SPIxSR and data transmission/reception begins. The
user must make sure that the correct data is loaded into the SPIxBUF for transmission before the
frame sync pulse is received.
Note: The use of the SSx and SCKx pins are mandatory in all Framed SPI modes.
Note: Receiving a frame sync pulse will start a transmission, regardless of whether data
was written to SPIxBUF. If no write was performed, the old contents of either
SPIxTXB (Standard mode) or the FIFO transmit buffer (Enhanced mode) will be
transmitted.

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