Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2010 Microchip Technology Inc. Preliminary DS39735A-page 47-41
Section 47. Motor Control PWM
Motor Control
PWM
47
Example 47-7: Code for Using the MCPWM Output Override Feature
47.14.1.1 OVERRIDE CONTROL FOR COMPLEMENTARY OUTPUT MODE
The PWM module does not allow certain overrides when a pair of PWM I/O pins are operating in
Complementary PWM Output mode (PMOD<3:1> = 0). The module does not allow both pins in
the output pair to become active simultaneously. The high-side pin in each output pair always
takes priority.
47.14.1.2 OVERRIDE SYNCHRONIZATION
If the Output Override Synchronization (OSYNC = 1) bit is set (PWMxCON2<1>), all output
overrides performed using the PxOVDCON register will be synchronized to the PWM time base.
Synchronous output overrides will occur at the following times:
Edge-Aligned mode when PxTMR is zero
Center-Aligned modes when PxTMR is zero
When the value of PxTMR matches PxTPER
The override synchronization function, when enabled, can be used to avoid unwanted narrow
pulses on the PWM output pins.
47.14.1.3 OUTPUT OVERRIDE EXAMPLES
Figure 47-23 shows an example of a waveform that might be generated using the PWM output
override feature. This figure also shows a six-step commutation sequence for a BLDC motor.
The motor is driven through a 3-phase inverter, as shown in Figure 47-24. When the
appropriate rotor position is detected, the PWM outputs are switched to the next commutation
state in the sequence. In this example, the PWM outputs are driven to specific logic states. The
PxOVDCON register values used to generate the signals in Figure 47-23 are given in
Table 47-5.
The PWM Duty Cycle registers can be used in conjunction with the PxOVDCON register. The
Duty Cycle registers control the current delivered to the load and the PxOVDCON register
controls the commutation. Such an example is shown in Figure 47-24. The PxOVDCON
register values used to generate the signals in Figure 47-24 are given in Table 47-6.
Note: Dead-time insertion is still performed when PWM channels are overridden manually.
/* Output Override Synchronization */
/* Output overrides via the P1OVDCON register are synchronized to the PWM */
/* time base by setting the OSYNC bit */
PWM1CON2bits.OSYNC = 1;
/* Override control register configuration */
/* Output on the PWM1H3:PWM1H1 and PWM1L3:PWM1L1 I/O pins are controlled */
/* by the corresponding POUT3H:POUT1L bits in the P1OVDCON register */
P1OVDCONbits.POVD3H = 0;
P1OVDCONbits.POVD2H = 0;
P1OVDCONbits.POVD1H = 0;
P1OVDCONbits.POVD3L = 0;
P1OVDCONbits.POVD2L = 0;
P1OVDCONbits.POVD1L = 0;
/* PWM I/O pins are driven to active state by setting the corresponding bit */
P1OVDCONbits.POUT3H = 1;
P1OVDCONbits.POUT2H = 1;
P1OVDCONbits.POUT1H = 1;
P1OVDCONbits.POUT3L = 1;
P1OVDCONbits.POUT2L = 1;
P1OVDCONbits.POUT1L = 1;
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section47-Motor_Control_PWM.pdf