Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2006 Microchip Technology Inc. Advance Information DS39703A-page 2-19
Section 2. CPU
CPU
2
4. 1 Instruction Word, 2 Instruction Cycles Table Operations:
These instructions will suspend fetching to insert a read or write cycle into the program
memory. The instruction fetched while executing the table operation is saved for one cycle
and executed in the cycle immediately after the table operation as shown in Example 2-9.
Example 2-9: Instruction Flow – Table Operations
5. 2 Instruction Words, 2 Instruction Cycles (GOTO, CALL):
In these instructions, the fetch after the instruction contains data. This results in a 2-cycle
instruction as shown in Example 2-10. The second word of a 2-word instruction is encoded,
so that it will be executed as a NOP, should it be fetched by the CPU without first fetching the
first word of the instruction. This is important when a 2-word instruction is skipped by a skip
instruction (see Example 2-13).
Example 2-10: Instruction Flow – 2-Word, 2-Cycle
6. Address Register Dependencies:
These are instructions that are subjected to a stall due to a data address dependency
between the data space read and write operations. An additional cycle is inserted to resolve
the resource conflict as discussed in Section 2.11 “Address Register Dependencies”.
Example 2-11: Instruction Flow – 1-Word, 1-Cycle (With Instruction Stall)
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOV #0x1234, W0
Fetch 1 Execute 1
2. TBLRDL.w [W0++], W1
Fetch 2 Execute 2
3. MOV #0x00AA, W1
Fetch 3 PM Data
Read Cycle
Bus Read Execute 3
4. MOV #0x00CC, W0
Fetch 4 Execute 4
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOV #0xAA55, W0
Fetch 1 Execute 1
2. GOTO LABEL
Fetch 2L Update PC
Fetch 2H
Forced NOP
3. LABEL: MOV W0, W2
Fetch 3 Execute 3
4. BSET PORTA, #3
Fetch 4 Execute 4
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOV W0, W1
Fetch 1 Execute 1
2. MOV [W1], [W4]
Fetch 2 Execute 1
Stall Execute 2
3. MOV W2, W1
Fetch 3 Execute 3

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