Vault 7: Projects
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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 190 © 2005-2011 Microchip Technology Inc.
COM
Complement Ws
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} COM{.B} Ws, Wd
[Ws], [Wd]
[Ws++], [Wd++]
[Ws--], [Wd--]
[++Ws], [++Wd]
[--Ws], [--Wd]
Operands: Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]
Operation: (Ws)
→Wd
Status Affected: N, Z
Encoding: 1110 1010 1Bqq qddd dppp ssss
Description: Compute the 1’s complement of the contents of the source register Ws
and place the result in the destination register Wd. Either register direct or
indirect addressing may be used for both Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
COM.B [W0++], [W1++] ; COM [W0] and store to [W1] (Byte mode)
; Post-increment W0, W1
Before
Instruction
After
Instruction
W0 2301 W0 2302
W1 2400 W1 2401
Data 2300 5607 Data 2300 5607
Data 2400 ABCD Data 2400 ABA9
SR 0000 SR 0008 (N = 1)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf