Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 6 2014 Microchip Technology Inc.
Register 2-1: SPIxSTAT: SPIx Status and Control Register
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
SPIEN
— SPISIDL — — SPIBEC2
(1)
SPIBEC1
(1)
SPIBEC0
(1)
bit 15 bit 8
R/W-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R-0, HS, HC
SRMPT SPIROV SRXMPT SISEL2
(1)
SISEL1
(1)
SISEL0
(1)
SPITBF SPIRBF
bit 7 bit 0
Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit HS = Hardware Settable bit C = Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SPIEN: SPIx Enable bit
1 = SPIx module is enabled and configures the SCKx, SDOx, SDIx and SSx
pins as serial port pins
0 = SPIx module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SPISIDL: SPIx Stop in Idle Mode bit
1 = SPIx module operation is discontinued when the device enters Idle mode
0 = SPIx module operation is continued in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
(1)
Master mode:
Number of SPIx transfers are pending.
Slave mode:
Number of SPIx transfers are unread.
bit 7 SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = The SPIx Shift register is empty and ready to send or receive data
0 = The SPIx Shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit
1 = A new word/byte is completely received and discarded; the user application has not read the
previous data in the SPIxBUF register
0 = No overflow has occurred
bit 5 SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
(1)
111 = Interrupt when the SPIx transmit buffer is full (the SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPIxSR, and as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR, and as a result, the TX FIFO has one open
memory location
011 = Interrupt when the SPIx receive buffer is full (the SPIRBF bit set)
010 = Interrupt when the SPIx receive buffer is three-fourth or more full
001 = Interrupt when the data bit is received in the receive buffer (the SRMPT bit is set)
000 = Interrupt when the last data bit in the receive buffer is read, and as a result, the buffer is empty
(the SRXMPT bit is set)
Note 1: These bits are not implemented on the dsPIC33/PIC24 devices as they do not support the
Enhanced Buffer mode.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf