Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39703A-page 2-24 Advance Information © 2006 Microchip Technology Inc.
2.11.2.2 INSTRUCTION STALL CYCLES AND FLOW CHANGE INSTRUCTIONS
The CALL and RCALL instructions write to the stack using W15 and may, therefore, force an
instruction stall prior to the next instruction if the source read of the next instruction uses W15.
The RETFIE and RETURN instructions can never force an instruction stall prior to the next
instruction because they only perform read operations. However, the user should note that the
RETLW instruction could force a stall because it writes to a W register during the last cycle.
The GOTO and branch instructions can never force an instruction stall because they do not
perform write operations.
2.11.2.3 INSTRUCTION STALLS AND REPEAT LOOPS
Other than the addition of instruction stall cycles, RAW data dependencies will not affect the
operation of REPEAT loops.
The prefetched instruction within a REPEAT loop does not change until the loop is complete or
an exception occurs. Although register dependency checks occur across instruction boundaries,
the PIC24F effectively compares the source and destination of the same instruction during a
REPEAT loop.
2.11.2.4 INSTRUCTION STALLS AND PROGRAM SPACE VISIBILITY (PSV)
When Program Space Visibility (PSV) is enabled and the Effective Address (EA) falls within the
visible PSV window, the read or write cycle is redirected to the address in program space.
Accessing data from program space takes up to 3 instruction cycles.
Instructions operating in PSV address space are subject to instruction stalls, just like any other
instruction. Although the instruction stall and PSV cycles both occur at the beginning of an
instruction, it is not possible to combine them. If a stall occurs coincidentally with a PSV cycle,
the stall cycle will be forced first, then the PSV cycle and finally, the instruction cycle.
Consider the following code segment:
ADD W0, [W1], [W2++] ; PSV = 1, W1=0x8000, PSVPAG=0xAA
MOV [W2], [W3]
This sequence of instructions would take five instruction cycles to execute. Two instruction cycles
are added to perform the PSV access via W1. Furthermore, an instruction stall cycle is inserted
to resolve the RAW data dependency caused by W2.
During a stalled instruction, the ROM Latch is transferred to the IR on the rising Q1 of the first
cycle, and the Flash data read is transferred to the ROM Latch on the rising Q3 of the 2nd cycle
of the instruction, as shown in Figure 2-9.

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