Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39737A-page 49-36 Preliminary © 2010 Microchip Technology Inc.
49.9 SAMPLE AND CONVERSION SEQUENCE EXAMPLES
The following configuration examples show the A/D operation in different sampling and buffering
configurations. In each example, setting the ASAM bit starts automatic sampling. A conversion
trigger ends sampling and starts conversion.
49.9.1 Sampling and Converting a Single Channel Multiple Times
Figure 49-19 and Table 49-12 illustrate a basic configuration of the ADC. In this case, one ADC
input, AN0, is sampled by one S&H channel, CH0, and converted. The results are stored in the
ADC buffer (ADC1BUF0-ADC1BUFF). This process repeats 16 times until the buffer is full and
then the ADC module generates an interrupt. The entire process then repeats.
The CHPS bits specify that only S&H CH0 is active. With ALTS clear, only the MUXA inputs are
active. The CH0SA bits and CH0NA bit are specified (AN0-AVss) as the input to the S&H
channel. All other input selection bits are not used.
Figure 49-19: Converting One Channel 16 Times/Interrupt
ADC Clock
SAMP
ADC1BUF0
TSAMP
TCONV
ADC1BUF1
DONE
ADC1BUF2
ADC1BUFF
Input to CH0
AN0
TSAMP
TCONV
AN0
TSAMP
TCONV
AN0
TSAMP
TCONV
AN0
AD1IF
ASAM
Conversion
Trigger

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh