Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2006 Microchip Technology Inc. Advance Information DS39707A-page 8-9
Section 8. Interrupts
Interrupts
8
8.3 INTERRUPT PROCESSING TIMING
8.3.1 Interrupt Latency for One-Cycle Instructions
Figure 8-3 shows the sequence of events when a peripheral interrupt is asserted during a
one-cycle instruction. The interrupt process takes four instruction cycles. Each cycle is numbered
in Figure 8-3 for reference.
The interrupt flag status bit is set during the instruction cycle after the peripheral interrupt occurs.
The current instruction completes during this instruction cycle. In the second instruction
cycle after the interrupt event, the contents of the PC and SRL registers are saved into a
temporary buffer register. The second cycle of the interrupt process is executed as a NOP to
maintain consistency with the sequence taken during a two-cycle instruction (see Section 8.3.2
“Interrupt Latency for Two-Cycle Instructions”). In the third cycle, the PC is loaded with the
vector table address for the interrupt source and the starting address of the ISR is fetched. In the
fourth cycle, the PC is loaded with the ISR address. The fourth cycle is executed as a NOP while
the first instruction in the ISR is fetched.
Figure 8-3: Interrupt Timing During a One-Cycle Instruction
4 6 6 64 4
INST(PC – 2) INST(PC) FNOP FNOP ISR
INST
Executed
Interrupt Flag
PUSH low 16 bits of PC
PUSH SRL and high 8 bits of PC
64
ISR + 2 ISR + 4
CPU Priority
Fetch
2000 (ISR) 2002 2004 2006PC PC + 2PC
Vector
Save PC in
Status bit
Vector#
Peripheral interrupt event
occurs at or before midpoint
TCY
1
2
3
4
temporary
buffer.
of this cycle.
(from temporary buffer).
(from temporary buffer).
Note: Where FNOP is a forced NOP instruction automatically inserted by the CPU.

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