Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2006 Microchip Technology Inc. Advance Information DS39707A-page 8-11
Section 8. Interrupts
Interrupts
8
8.3.3 Returning from Interrupt
The “Return from Interrupt” instruction, RETFIE, exits an interrupt or trap routine.
During the first cycle of a RETFIE instruction, the upper bits of the PC and the SRL register are
popped from the stack. The lower 16 bits of the stacked PC value are popped from the stack
during the second cycle. The third instruction cycle is used to fetch the instruction addressed by
the updated program counter. This cycle executes as a NOP.
Figure 8-6: Return from Interrupt Timing
4
4
4
4
6
6
CPU
Priority
RETFIE
RETFIE
PC
INST
Executed
FNOP
ISR Last
6
PC + 2 PC + 4
POP low 16 bits of PC to RAM Stack.
POP SRL and high 8 bits of PC.
PC PC + 2 PC + 4 PC + 6ISR ISR + 2PC
2nd cycle
TCY
Instruction

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