Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2007 Microchip Technology Inc. Advance Information DS39715A-page 4-9
Section 4. Program Memory
Program
Memory
4
4.4.2 PSV Timing
Instructions that use PSV will require two extra instruction cycles to complete execution, except
all MOV instructions (including the MOV.D instruction) that require only one extra cycle to complete
execution.
The additional instruction cycles are used to fetch the PSV data on the program memory bus.
4.4.2.1 USING PSV IN A REPEAT LOOP
Instructions that use PSV within a REPEAT loop eliminate the extra instruction cycle(s) required
for the data access from program memory, hence incurring no overhead in execution time.
However, the following iterations of the REPEAT loop will incur an overhead of two instruction
cycles to complete execution:
The first iteration.
The last iteration.
Instruction execution prior to exiting the loop due to an interrupt.
Instruction execution upon re-entering the loop after an interrupt is serviced.
4.4.2.2 PSV AND INSTRUCTION STALLS
Refer to Section 2. “CPU” for more information about instruction stalls using PSV.
4.5 PROGRAM MEMORY WRITES
This section describes the programming technique for Flash program memory. The PIC24F
devices have an internal programmable Flash memory for execution of user code. There are two
methods to program this memory:
Run-Time Self-Programming (RTSP)
In-Circuit Serial Programming™ (ICSP™)
Enhanced In-Circuit Serial Programming (EICSP)
JTAG Programming
RTSP is performed by the user’s software. ICSP and EICSP are performed using a serial data
connection to the device and allow much faster programming time than RTSP. RTSP techniques
are described in this section.
The ICSP and EICSP protocols are defined in the
“PIC24FJXXXGA0XX Flash Programming
Specification”
(DS39768), which can to be downloaded from the Microchip web site
(www.microchip.com). The JTAG programming is defined in the programming section of the
IEEE 1149.1-2001,
“IEEE Standard Test Access Port and Boundary Scan Architecture”
.

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