Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
PIC24F Family Reference Manual
DS39699B-page 23-27 Advance Information © 2007 Microchip Technology Inc.
Figure 23-18: SPIx Module Master Mode Timing Characteristics (CKE = 1)
Table 23-4: SPIx Module Master Mode Timing Requirements (CKE = 1)
AC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ T
A ≤ +85°C for Industrial
Param
No.
Symbol Characteristic Min Typ
(1)
Max Units Conditions
SP10 TscL SCKx Output Low Time
(2)
TCY/2 — — ns
SP11 TscH SCKx Output High Time
(2)
TCY/2 — — ns
SP20 TscF SCKx Output Fall Time
(3)
— 10 25 ns
SP21 TscR SCKx Output Rise Time
(3)
— 10 25 ns
SP30 TdoF SDOx Data Output Fall Time
(3)
— 10 25 ns
SP31 TdoR SDOx Data Output Rise Time
(3)
— 10 25 ns
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
— — 30 ns
SP36 TdoV2sc,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
20 — — ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
20 — — ns
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP36
SP30,SP31
SP35
MSb
Bit 14 - - - - - -1
LSb In
Bit 14 - - - -1
LSb
SP11 SP10
SP21
SP20
SP41
MSb In
SP40
SP20
SP21
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section23-Serial_Peripheral_Interface.pdf