Vault 7: Projects
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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 254 © 2005-2011 Microchip Technology Inc.
INC
Increment f
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} INC{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: (f) + 1 → destination designated by D
Status Affected: DC, N, OV, Z, C
Encoding:
1110 1100 0BDf ffff ffff ffff
Description: Add one to the contents of the file register, and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG. If
WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
INC.B 0x1000 ; Increment 0x1000 (Byte mode)
Before
Instruction
After
Instruction
Data 1000 8FFF Data 1000 8F00
SR 0000 SR 0101 (DC, C = 1)
Example 2:
INC 0x1000, WREG ; Increment 0x1000 and store to WREG
; (Word mode)
Before
Instruction
After
Instruction
WREG ABCD WREG 9000
Data 1000 8FFF Data 1000 8FFF
SR 0000 SR 0108 (DC, N = 1)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf