Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2011 Microchip Technology Inc. DS39712D-page 7-7
Section 7. Reset
Reset
7
Code execution is delayed further by a small delay, designated as TRST. The TRST delay is
required to transfer the configuration values from the Flash Configuration Words (FCW) in the
program memory into the Configuration registers, which occurs after any device Reset. SYSRST
is released and the device is no longer held in Reset, but the device clocks are prevented from
running during T
RST, as depicted in Figure 7-2. Once all of the delays have expired, the system
clock is released and code execution can begin.
Refer to Section 7.16 “Electrical Specifications” for more information on the values of the
delay parameters.
Figure 7-2: POR Module Timing Sequence for Rising V
DD
TPOR
VDD
VPOR
POR Circuit Threshold Voltage
SYSRST
TSTARTUP
(1)
Internal Power-on Reset Pulse Occurs
and Begins POR Delay Time, T
POR
POR Circuit is Initialized at VPOR
Time
System Clock is Started
After T
STARTUP Delay
Expires
T
RST
System Clock is Released
and Code Execution
Begins
POR
PWRT
System Clock
Note 1: T
VREG, if the on-chip regulator is enabled or TPWRT, if the on-chip regulator is disabled.
2: Timer and interval are determined by the initial start-up oscillator configuration; T
OSC is for external oscillator
modes, T
FRC is for the FRC oscillator or TLPRC for the internal 31 kHz RC oscillator.
(Note 2)
Oscillator Delay
(2)
System Reset is Released
After Clock is Stable
Note: When the device exits the Reset condition (begins normal operation), the device operating parameters
(voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device will not
function correctly. The user must ensure that the delay between the time power is first applied, and the time,
SYSRST
, becomes inactive is long enough to get all operating parameters within the specification.

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