Vault 7: Projects

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PIC24F Family Reference Manual
DS39737A-page 49-34 Preliminary © 2010 Microchip Technology Inc.
49.8 ADC CONFIGURATION FOR 1.1 Msps
When the device is running at 13.3 MIPS, the ADC module can be configured to sample at a
1.1 Msps throughput rate.
The ASAM bit (ADxCON1<2>) is set to ‘1to begin sampling automatically after the conversion
completes. The internal counter, which ends sampling and starts conversion, is set as the sample
clock source by setting the SSRC<2:0> bits = 111 (ADxCON1<7:5>). The system clock is
selected to be the ADC conversion clock by setting the ADRC bit to 0(ADxCON3<15>). The
automatic sample time bit is set to less than 12 T
AD. The ADC conversion time is configured to
75 ns by setting the ADCS<7:0> bits to 00000000 (ADxCON3<7:0>), as calculated in
Equation 49-7.
Equation 49-6: ADC Conversion Time When Running at 13.3 MIPS
The ADC conversion time will be 12 T
AD, as calculated in Equation 49-7.
Equation 49-7: ADC Conversion Time
The ADC channels, CH0 and CH1 (CHPS<1:0> = 01), are set up to convert analog input AN0 or
AN3 (only one at any time) in Sequential mode (SIMSAM = 0). Figure 49-18 illustrates the
sampling sequence.
Figure 49-18: Sampling Sequence for 1.1 Msps
The samples are transferred to ADC1BUF0-ADC1BUFF at a rate of 1.1 Msps. The data can be
processed by accessing half of the buffers at a time by setting the BUFS bit.
TAD = TCY * (ADCS<7:0> + 1) = (1/13.3M) * 1 = 75 ns (13.3 MHz)
TCONV = 12 * TAD = 900 ns (1.1 MHz)
Sample 1 ANx
Sample 2 ANx
CH0
CH1
Convert 1 ANx
Convert 2 ANx
SOC
Trigger
Sample 4 ANx
Convert 3 ANx
Convert 4 ANx
Sample 3 ANx Sample 5 ANx
T T T T
Note: The ‘x’ in ANx is either 0 or 3. T is 900 ns and the frequency is 1.1 Msps.

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