Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39707A-page 8-18 Advance Information © 2006 Microchip Technology Inc.
Register 8-9: IPCn: Interrupt Priority Registers 0 Through 28 (Interrupt Vectors 0 Through 115)
(1
)
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
V(4n + 3)IP2 V(4n + 3)IP1 V(xn + 3)IP0 V(4n + 2)IP2 V(4n + 2)IP1 V(4n + 2)IP0
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
V(4n + 1)IP2 V(4n + 1)IP1 V(xn + 1)IP0 V(4n)IP2 V(4n)IP1 V(4n)IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at any Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14-12 V(4n + 3)IP2:V(4n + 3)IP0: Interrupt Priority bits for Interrupt Vector 4n + 3
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0
bit 10-8 V(4n + 2)IP2:V(4n + 2)IP0: Interrupt Priority bits for Interrupt Vector 4n + 2
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0
bit 6-4 V(4n + 1)IP2:V(4n + 1)IP0: Interrupt Priority bits for Interrupt Vector 4n + 1
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0
bit 2-0 V(4n)IP2:V(4n)IP0: Interrupt Priority bits for Interrupt Vector 4n
111 = Interrupt is priority 7 (highest priority interrupt)
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Note 1: Not all interrupt vectors are implemented on all devices. Refer to the Interrupt Vector Table for the specific
device or family data sheet to verify where interrupt vectors are implemented for a specific device.

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