Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2010-2013 Microchip Technology Inc. DS39881E-page 35
TABLE 4-6: TIMER REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
TMR1 0100 Timer1 Register
PR1 0102 Timer1 Period Register
T1CON 0104 TON
TSIDL TGATE TCKPS1 TCKPS0 TSYNC
TMR2 0106 Timer2 Register
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)
TMR3 010A Timer3 Register
PR2 010C Timer2 Period Register
PR3 010E Timer3 Period Register
T2CON 0110 TON
TSIDL TGATE TCKPS1 TCKPS0 T32 T
T3CON 0112 TON
TSIDL TGATE TCKPS1 TCKPS0 T
TMR4 0114 Timer4 Register
TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only)
TMR5 0118 Timer5 Register
PR4 011A Timer4 Period Register
PR5 011C Timer5 Period Register
T4CON 011E TON
TSIDL TGATE TCKPS1 TCKPS0 T32 T
T5CON 0120 TON
TSIDL TGATE TCKPS1 TCKPS0 T
Legend: = unimplemented, read as 0. Reset values are shown in hexadecimal.
TABLE 4-7: INPUT CAPTURE REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
IC1BUF 0140 Input Capture 1 Register
IC1CON 0142
ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2
IC2BUF 0144 Input Capture 2 Register
IC2CON 0146
ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2
IC3BUF 0148 Input Capture 3 Register
IC3CON 014A
ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2
IC4BUF 014C Input Capture 4 Register
IC4CON 014E
ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2
IC5BUF 0150 Input Capture 5 Register
IC5CON 0152
ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2
Legend: = unimplemented, read as 0. Reset values are shown in hexadecimal.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004.pdf