Vault 7: Projects
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© 2005-2011 Microchip Technology Inc. DS70157F-page 437
Section 5. Instruction Descriptions
Instruction
Descriptions
5
XOR
Exclusive OR f and WREG
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} XOR{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: (f).XOR.(WREG) → destination designated by D
Status Affected: N, Z
Encoding: 1011 0110 1BDf ffff ffff ffff
Description: Compute the logical exclusive OR operation of the contents of the
default working register WREG and the contents of the specified file
register and place the result in the destination register. The optional
WREG operand determines the destination register. If WREG is
specified, the result is stored in WREG. If WREG is not specified, the
result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
XOR.B 0x1FFF ; XOR (0x1FFF) and WREG (Byte mode)
; Store result to 0x1FFF
Before
Instruction
After
Instruction
WREG (W0) 7804 WREG (W0) 7804
Data 1FFE 9439 Data 1FFE 9039
SR 0000 SR 0008 (N = 1)
Example 2:
XOR 0xA04, WREG ; XOR (0xA04) and WREG (Word mode)
; Store result to WREG
Before
Instruction
After
Instruction
WREG (W0) 6234 WREG (W0) C267
Data 0A04 A053 Data 0A04 A053
SR 0000 SR 0008 (N = 1)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf