Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 140 © 2005-2011 Microchip Technology Inc.
BRA LTU
Branch if Unsigned Less Than
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} BRA LTU, Expr
Operands: Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].
Operation: Condition = !C
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register
Status Affected: None
Encoding: 0011 1001 nnnn nnnn nnnn nnnn
Description: If the Carry flag is ‘0’, then the program will branch relative to the next PC.
The offset of the branch is the two’s complement number ‘2 * Slit16’,
which supports branches up to 32K instructions forward or backward. The
Slit16 value is resolved by the linker from the supplied label, absolute
address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).
Note : This instruction is identical to the BRA NC, Expr (Branch if Not
Carry) instruction and has the same encoding. It will reverse
assemble as BRA NC, Slit16.
Words: 1
Cycles: 1 (2 if branch taken) – PIC24F, PIC24H, dsPIC30F, dsPIC33F
1 (4 if branch taken) – PIC24E, dsPIC33E
Example 1:
002000 HERE: BRA LTU, BYPASS
002002 NO_LTU: . . .
002004 . . .
002006 . . .
002008 . . .
00200A GOTO THERE
00200C BYPASS: . . .
00200E . . .
; If LTU, branch to BYPASS
; Otherwise... continue
Before
Instruction
After
Instruction
PC 00 2000 PC 00 2002
SR 0001 (C = 1) SR 0001 (C = 1)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf