Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2009 Microchip Technology Inc. DS39700C-page 6-27
Section 6. Oscillator
Oscillator
6
A recommended code sequence for a clock switch includes the following:
1. Disable interrupts during the OSCCON register unlock and write sequence.
2. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to
OSCCON<15:8> in two back-to-back instructions.
3. Write new oscillator source to NOSC control bits in the instruction immediately following
the unlock sequence.
4. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
5. Set the OSWEN bit in the instruction immediately following the unlock sequence.
6. Continue to execute code that is not clock-sensitive (optional).
7. Invoke an appropriate amount of software delay (cycle counting) to allow the selected
oscillator and/or PLL to start and stabilize.
8. Check to see if OSWEN is ‘0’. If it is, the switch was successful.
The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in
Example 6-1.
Example 6-1: Basic Code Sequence for Clock Switching
6.11.2.1 CLOCK SWITCHING CONSIDERATIONS
When incorporating clock switching into an application, users should keep certain things in mind
when designing their code.
• The OSCCON unlock sequence is extremely timing-critical. The OSCCON register byte is
only writable for one instruction cycle following the sequence. Some high-level languages,
such as C, may not preserve the timing-sensitive sequence of instructions when compiled.
When clock switching is required for an application written in a high-level language, it is
best to create the routine in assembler and link it to the application, calling it as a function
when it is required.
• If the destination clock source is a crystal oscillator, the clock switch time will be dominated
by the oscillator start-up time.
• If the new clock source does not start, or is not present, the clock switching hardware will
wait indefinitely for the new clock source. The user can detect this situation because the
OSWEN bit remains set indefinitely.
• If the new clock source uses the PLL, a clock switch will not occur until lock has been
achieved. The user can detect a loss of PLL lock because the LOCK bit will be cleared and
the OSWEN bit is set.
• Switching to a low-frequency clock source, such as the Secondary Oscillator, will result in
very slow device operation.
Note: The application should not attempt to switch to a clock with a frequency lower than
100 kHz when the FSCM is enabled. Clock switching in these instances may generate
a false oscillator fail trap and result in a switch to the Internal Fast RC Oscillator.
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV #OSCCONH,w1
MOV #0x78, w2
MOV #0x9A, w3
MOV.b w2, [w1]
MOV.b w3, [w1]
;Set new oscillator selection
MOV.b WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
MOV #OSCCONL,w1
MOV.b #0x01, w0
MOV #0x46, w2
MOV #0x57, w3
MOV.b w2, [w1]
MOV.b w3, [w1]
;Start oscillator switch operation
MOV.b w0, [w1]
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section6-Oscillator.pdf