Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2014 Microchip Technology Inc. DS70005185A-page 25
Serial Peripheral Interface (SPI) Module
3.4.2 ENHANCED BUFFER SLAVE MODE
In Enhanced Buffer Slave mode, the data is transmitted and received as the external clock pulses
appear on the SCKx pin. The CKP (SPIxCON1<6>) and CKE (SPIxCON1<8>) bits determine on
which edge of the clock data transmission occurs.
The rest of the operation of the module is identical to that in Master mode. Specific timings for
Enhanced Buffer Slave mode operations are identical to those for Standard Slave mode, as
shown in Figure 3-3 through Figure 3-5.
To set up the SPIx module for the Enhanced Buffer Slave mode of operation, complete the
following steps:
1. Clear the SPIxBUF register.
2. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx register.
b) Select an Interrupt mode using the SISEL<2:0> bits (SPIxSTAT<4:2>).
c) Set the SPIxIE bit in the respective IECx register.
d) Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
3. When MSTEN (SPIxCON1<5>) = 0, write the desired settings to the SPIxCON1 and
SPIxCON2 registers.
4. Clear the SMP bit (SPIxCON1<9>).
5. If the CKE bit is set, the SSEN bit (SPIxCON1<7>) must be set, therefore enabling the
SSx
pin.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>).
8. Enable the SPIx operation by setting the SPIEN bit (SPIxSTAT<15>).
3.4.2.1 Slave Select Synchronization
The SSx pin allows a Synchronous Slave mode. If the SSEN bit (SPIxCON1<7>) is set,
transmission and reception are enabled in Slave mode only if the SSx
pin is driven to a low state
(see Figure 3-4). The port output or other peripheral outputs must not be driven in order to allow
the SSx
pin to function as an input. If the SSEN bit is set and the SSx pin is driven high, the SDOx
pin is no longer driven and will tri-state, even if the module is in the middle of a transmission. An
aborted transmission will be retried the next time the SSx pin is driven low using the data held in
the SPIxTXB register. If the SSEN bit is not set, the SSx
pin does not affect the module operation
in Slave mode.
3.4.2.2 SPITBF Status Flag Operation
The function of the SPITBF bit (SPIxSTAT<1>) is different in the Slave mode of operation. If the
SSEN bit is cleared, the SPITBF bit is set when the last available buffer location is loaded by the
user application. It is cleared when the module transfers data from the buffer to the SPIxSR
register and a buffer location is available for a CPU write. This is similar to the SPITBF bit function
in Master mode.
If the SSEN bit is set, the SPITBF bit is set when the last available buffer location is loaded by
the user application. However, it is cleared only when the SPIx module completes data
transmission, leaving a buffer location available for a CPU write. A transmission will be aborted
when the SSx
pin goes high. Each data word is held in the buffer until all bits are transmitted to
the receiver.
Note: In Slave mode, the SPIx clock frequency on the SCKx pin must be lower than the
device system frequency (F
SCK < FCY).
Note: To meet the module timing requirements, the SSx pin must be enabled in Slave
mode when CKE = 1 (see Figure 3-5).
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf