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© 2010 Microchip Technology Inc. Preliminary DS39737A-page 49-21
Section 49. 10-Bit ADC with 4 Simultaneous Conversions
10-Bit ADC with
4 Simultaneous
Conversions
49
49.4 ADC CONFIGURATION
49.4.1 ADC Channel Selection
The user application can select 1-Channel (CH0), 2-Channel (CH0, CH1) or 4-Channel mode
(CH0-CH3) using the Channel Select bits (CHPS<1:0>) in the ADC Control Register 2
(ADxCON2<9:8>).
Table 49-5: 10-Bit ADC Channel Selection
49.4.2 ADC Clock Selection
The ADC module can be clocked from the instruction cycle clock (TCY) or by using the dedicated
internal RC clock (see Figure 49-12). When using the instruction cycle clock, a clock divider
drives the instruction cycle clock and allows a lower frequency to be chosen. The clock divider is
controlled by the ADC Conversion Clock Select bits (ADCS<7:0>) in the ADC Control Register 3
(ADxCON3<7:0>), which allows 64 settings, from 1:1 to 1:64, to be chosen.
For correct A/D conversion, the ADC clock period (T
AD) must be a minimum of 75 ns.
Equation 49-5 shows the ADC clock period (T
AD) as a function of the ADCS control bits and the
device instruction cycle clock period, T
CY.
Equation 49-5: ADC Clock Period
The ADC module has a dedicated internal RC clock source that can be used to perform
conversions. The internal RC clock source is used when A/D conversions are performed while
the device is in Sleep mode. The internal RC oscillator is selected by setting the ADC Conversion
Clock Source bit (ADRC) in the ADC Control Register 3 (ADxCON3<15>). When the ADRC bit
is set, the ADCS<7:0> bits have no effect on the ADC operation.
Figure 49-12: ADC Clock Generation
CHPS<1:0> Channel Selection
00 CH0
01 Dual Channel (CH0, CH1)
1x Multi-Channel (CH0-CH3)
Note: Refer to the specific device data sheet for ADRC frequency specifications.
If ADRC = 0
ADC Clock Period (TAD) = TCY • (ADCS + 1)
If ADRC = 1
ADC Clock Period (TAD) = TADRC
0
1
ADCS<7:0>
ADRC
ADC Clock (T
AD)
T
CY
ADC Internal RC
N
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section49-10-Bit_ADC_with_4_Simultaneous_Conversions.pdf