Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 24 2009-2013 Microchip Technology Inc.
7.4 Setup for UART Reception
The following steps are used to set up a UART reception:
1. Initialize the UxBRG register for the appropriate baud rate (see Section 3.0 “UART Baud
Rate Generator”).
2. Set the number of data bits, number of Stop bits and parity selection by writing to the
PDSEL<1:0> (UxMODE<2:1>) and STSEL (UxMODE<0>) bits.
3. If interrupts are desired, set the UxRXIE bit in the corresponding Interrupt Enable
Control x register (IECx).
Specify the interrupt priority for the interrupt using the UxRXIP<2:0> control bits in the cor-
responding Interrupt Priority Control x register (IPCx). Also, select the Receive Interrupt
mode by writing to the URXISEL<1:0> bits (UxSTA<7:6>).
4. Enable the UART module by setting the UARTEN bit (UxMODE<15>).
5. Receive interrupts will depend on the URXISEL<1:0> control bit settings.
If receive interrupts are not enabled, the user application can poll the URXDA bit. The
UxRXIF bit should be cleared in the software routine that services the UART receive
interrupt.
6. Read data from the receive buffer.
If 9-bit transmission is selected, read a word; otherwise, read a byte. The URXDA status
bit (UxSTA<0>) is set whenever the data is available in the buffer.
Example 7-1 provides the sample code that sets up the UART for reception.
Figure 7-2: UARTx Reception
(1,2)
Figure 7-3: UARTx Reception with Receive Overrun
Start
bit bit 1bit 0 bit 7 bit 0Stop
bit
Start
bit bit 7 Stop
bit
UxRX
RIDLE bit
Character 1
to UxRXREG
Character 2
to UxRXREG
UxRXIF
(URXISEL<1:0> =
0x
)
Note 1: This timing diagram shows two characters received on the UxRX input.
2: If the interrupt flag is used by the application software as a basis for disabling the UART transmission, the software should
wait for 1-bit time before disabling the transmission.
Start
bit bit 7/8bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit
Start
bitbit 7/8 Stop
bit
UxRX
OERR bit
RIDLE bit
Characters 1, 2, 3 and 4
Stored in Receive FIFO
Character 5
Held in UxRSR
Stop
bit
Character 1 Characters 2, 3, 4 and 5 Character 6
OERR Cleared by User in Software
Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the
Receive Shift register. An overrun error occurs at the start of the 6th character.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-PIC24FJ32MC102-UART.pdf