Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

2007-2014 Microchip Technology Inc. DS70000195F-page 3
Inter-Integrated Circuit™ (I
2
C™)
Figure 1-1: I
2
C™ Block Diagram
I2CxRCV
Internal
Data Bus
SCLx
SDAx
Shift
Match Detect
Clock
Address Match
Clock
Stretching
I2CxTRN
LSB
Shift Clock
BRG
Reload
Control
TCY or TCY/2
(1)
Acknowledge
Generation
I2CxCONH
I2CxSTAT
Control Logic
Read
LSB
Write
Read
I2CxBRG
I2CxRSR
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Down Counter
I2CxCONL
Write
Read
Note 1: Refer to specific device data sheet for the clock rate.
I2CxADD
Start and Stop
Bit Detect
Start and Stop
Bit Generation
Collision
Detect
I2CxMSK

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