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PIC24F Family Reference Manual
DS39735A-page 47-44 Preliminary © 2010 Microchip Technology Inc.
47.14.3 PWM Update Lockout
In some applications, it is important that all duty cycle and period registers be written before
the new values take effect. The update disable feature allows the user application to specify
when new duty cycle and period values can be used by the module. The PWM update lockout
feature is enabled by setting the PWM Update Disable (UDIS) bit in the PWM Control
Register 2 (PWMxCON2<0>) SFR.
The UDIS bit affects all duty cycle registers, PxDC3:PxDC1, and the PWM time base period
buffer, PxTPER. To execute an update lockout, perform the following steps:
Set the UDIS bit
Write all duty cycle registers and PxTPER, if applicable
Clear the UDIS bit to re-enable updates
47.14.4 Write-Protected Registers
If the PWMLOCK input signal is asserted (PWMLOCK = 1), the PWMxCON1, PxFLTACON and
PxFLTBCON registers are write-protected. To gain write access to these locked registers, the
user must write two consecutive values (0xABCD and 0x4321) to the PWMKEY register to
perform the unlock operation. The write access to the PWM1CON1, PxFLTACON or
PxFLTBCON registers must be the next SFR access following the unlock process. There can be
no other SFR accesses during the unlock process and subsequent write access.
To write to all registers, the PWMxCON1, PxFLTACON and PxFLTBCON registers require three
unlock operations.
If the PWMLOCK input signal is deasserted (PWMLOCK = 0), the PWMKEY functionality is
disabled, and the PWMxCON1, PxFLTACON and PxFLTBCON registers may be written without
restrictions.
Note: Immediate updates must be disabled (IUE = 0) to use the PWM update lockout
feature.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section47-Motor_Control_PWM.pdf