Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2014 Microchip Technology Inc. DS70005185A-page 13
Serial Peripheral Interface (SPI) Module
Figure 3-1: SPIx Master/Slave Connection
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
LSb
MSb
SDIx
SDOx
PROCESSOR 2 (SPIx Slave)
SCKx
SSx
(1)
Serial Transmit Buffer
(SPIxTXB)
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1 (SPIx Master)
Serial Clock
SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
SSx
SCKx
Serial Transmit Buffer
(SPIxTXB)
MSTEN (SPIxCON1<5>) = 1
SPIx Buffer
(SPIxBUF)
(2,3)
SPIx Buffer
(SPIxBUF)
(2,3)
Note 1: The use of the SSx pin in Slave mode is optional.
2: The user application must write transmit data to read received data from the SPIxBUF register. The
SPIxTXB and SPIxRXB registers are memory-mapped to the SPIxBUF register.
3: If the user application does not change the data in the SPIxBUF register, every new transmission shifts the
SPIxBUF register value instead of shifting the value received in the Shift register.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf