Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2005-2011 Microchip Technology Inc. DS70157F-page 181
Section 5. Instruction Descriptions
Instruction
Descriptions
5
Example 2:
004200 CALL W7
004202 ...
. ...
005500 _TEST: INC W1, W2
005502 DEC W1, W3
. ...
; Call TEST subroutine indirectly
; using W7
; _TEST starts here
;
Before
Instruction
After
Instruction
PC 00 4200 PC 00 5500
W7 5500 W7 5500
W15 6F00 W15 6F04
Data 6F00 FFFF Data 6F00 4202
Data 6F02 FFFF Data 6F02 0000
SR 0000 SR 0000
CALL
Call Indirect Subroutine
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X
Syntax: {label:} CALL Wn
Operands:
Wn ∈ [W0 ... W15]
Operation:
(PC) + 2 → PC
(PC<15:1>) → TOS, SFA bit → TOS<0>
(W15) + 2 → W15
(PC<23:16>) → TOS
(W15) + 2 → W15
0 → SFA bit
0 → PC<22:16>
(Wn<15:1>) → PC<15:1>
NOP → Instruction Register
Status Affected:
SFA
Encoding: 0000 0001 0000 0000 0000 ssss
Description: Indirect subroutine call over the first 32K instructions of program memory.
Before the CALL is made, the 24-bit return address (PC + 2) is PUSHed
onto the stack. After the return address is stacked, Wn<15:1> is loaded
into PC<15:1> and PC<22:16> is cleared. Since PC<0> is always ‘0’,
Wn<0> is ignored.
The ‘s’ bits select the source register.
Words:
1
Cycles:
4
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf