Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39716A-page 33-6 Advance Information © 2006 Microchip Technology Inc.
The TAP controller on the PIC24F family devices is a synchronous finite state machine that
implements the standard 16 states for JTAG. Figure 33-3 shows all the module states of the TAP
controller. All Boundary Scan Test (BST) instructions and test results are communicated through
the TAP via the TDI pin in a serial format, Least Significant bit first.
Figure 33-3: TAP Controller Module State Diagram
By manipulating the state of TMS and the clock pulses on TCK, the TAP controller can be moved
through all of the defined module states to capture, shift and update various instruction and/or
data registers. Figure 33-3 shows the state changes on TMS as the controller cycles through its
state machine. Figure 33-4 shows the timing of TMS and TCK while transitioning the controller
through the appropriate module states for shifting in an instruction. In this example, the sequence
shown demonstrates how an instruction is read by the TAP controller.
All TAP controller states are entered on the rising edge of the TCK pin. In this example, the TAP
controller starts in the Test-Logic Reset state. Since the state of the TAP controller is dependent
on the previous instruction, and therefore could be unknown, it is good programing practice to
begin in the Test-Logic Reset state.
When TMS is asserted low on the next rising edge of TCK, the TAP controller will move into the
Run-Test/Idle state. On the next two rising edges of TCK, TMS is high; this moves the TAP
controller to the Select-IR-Scan state.
On the next two rising edges of TCK, TMS is held low; this moves the TAP controller into the
Shift-IR state. An instruction is shifted in to the Instruction Shift register via the TDI on the next
four rising edges of TCK. After the TAP controller enters this state, the TDO pin goes from a
high-impedance state to active. The controller shifts out the initial state of the Instruction Register
(IR) on the TDO pin, on the falling edges of TCK, and continues to shift out the contents of the
Instruction Register while in the Shift-IR state. The TDO returns to the high-impedance state on
the first falling edge of TCK upon exiting the shift state.
On the next three rising edges of TCK, the TAP controller exits the Shift-IR state, updates the
Instruction Register and then moves back to the Run-Test/Idle state. Data, or another instruction,
can now be shifted in to the appropriate Data or Instruction Register.
Test-Logic
Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit 1-DR
Pause-DR
Exit 2-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit 1-IR
Pause-IR
Exit 2-IR
Update-IR
TMS = 0TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
TMS = 0TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
TMS = 1TMS = 1
TMS = 0
TMS = 0
TMS = 0
TMS = 1
TMS = 1

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