Vault 7: Projects

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PIC24F Family Reference Manual
DS39741A-page 48-16 Preliminary © 2010 Microchip Technology Inc.
Figure 48-4: User Programmable Blanking Function Diagram
48.4.3 Digital Output Filter
In many motor and power control applications, the analog comparator input signals can be
corrupted by the large electromagnetic fields generated by the associated external switching
power transistors. Corruption of the analog input signals to the comparator can cause unwanted
comparator output transitions. The programmable digital output filter can minimize the effects of
input signal corruption.
The digital filter requires three consecutive input samples to be similar before the output of the
filter can change state. Assuming the current state is 0’, a string of inputs such
as ‘001010110111will only yield an output state of 1at the end of the example sequence after
the three consecutive 1’s. Similarly, a sequence of three consecutive 0’s are required before the
output will change to a zero state.
Because of the requirement of three similar consecutive states for the filter, the chosen digital
filter clock period must be one-third or less than the maximum desired comparator response time.
The digital filter is enabled by setting the CFLTREN bit (CMxFLTR<3>). The CFDIV<2:0> bits
(CMxFLTR<2:0>) select the clock divider ratio for the clock signal input to the digital filter block.
The CFSEL<2:0> bits (CMxFLTR<6:4>) select the desired clock source for the digital filter. The
digital filter is disabled (bypassed) following a system Reset.
SELSRCA<3:0>
SELSRCB<3:0>
SELSRCC<3:0>
AND
CMxMSKCON
MUX A
MAI
MBI
MCI
Analog Comparator Output
To Digital
Signals
Filter
OR
Blanking
Blanking
Blanking
Signals
Signals
ANDI
MASK
“AND-OR” function
MAI
MBI
MBI
MCI
MCI
HLMS
MAI
MUX BMUX C
Blanking
Logic

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