Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2005-2011 Microchip Technology Inc. DS70157F-page 287
Section 5. Instruction Descriptions
Instruction
Descriptions
5
Example 2:
MOV W11, [W1-0x400] ; store W11 to [W1-0x400]
; (Word mode)
Before
Instruction
After
Instruction
W1 1000 W1 1000
W11 8813 W11 8813
Data 0C00 FFEA Data 0C00 8813
SR 0000 SR 0000
MOV
Move Ws to Wd
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} MOV{.B} Ws, Wd
[Ws], [Wd]
[Ws++], [Wd++]
[Ws--], [Wd--]
[--Ws], [--Wd]
[++Ws], [++Wd]
[Ws + Wb], [Wd + Wb]
Operands: Ws ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]
Operation: (Ws) →Wd
Status Affected: None
Encoding:
0111 1www wBhh hddd dggg ssss
Description: Move the contents of the source register into the destination register.
Either register direct or indirect addressing may be used for Ws and Wd.
The ‘w’ bits define the offset register Wb.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘h’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘g’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.
2: When Register Offset Addressing mode is used for both the
source and destination, the offset must be the same because
the ‘w’ encoding bits are shared by Ws and Wd.
3: The instruction “PUSH Ws” translates to MOV Ws, [W15++].
4: The instruction “POP Wd” translates to MOV [--W15], Wd.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf