Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 24 2007-2014 Microchip Technology Inc.
5.3 Receiving Data from a Slave Device
The master can receive data from the slave device after the master has transmitted the slave
address with an R/W
status bit value of 1’. This is enabled by setting the RCEN bit (I2CxCON<3>
or I2CxCONL<3>). The master logic begins to generate clocks, and before each falling edge of
the SCLx, the SDAx line is sampled and data is shifted into the I2CxRSR register.
After the falling edge of the eighth SCLx clock, the following events occur:
The RCEN bit is automatically cleared
The contents of the I2CxRSR register transfer into the I2CxRCV register
The RBF status bit (I2CxSTAT<1>) is set
The I
2
C module generates the MI2CxIF interrupt
When the CPU reads the receive buffer (I2CxRCV), the RBF status bit is automatically cleared.
The user software can process the data and then execute an Acknowledge sequence.
The sequence of events that occurs during master transmission and master reception is
illustrated in Figure 5-4.
Figure 5-4: Master Reception Timing Diagram
Note: The lower 5 bits of the I2CxCON or I2CxCONL register must be 0’ before
attempting to set the RCEN bit. This ensures that the master logic is inactive.
D7 D6 D5 D4 D3 D2 D1 D0
SCLx (Master)
SCLx (Slave)
SDAx (Slave)
SDAx (Master)
RBF
I
2
C™ Bus State
MI2CxIF Interrupt
5 62 3 4
Writing the RCEN bit will start a master reception event. The BRG starts. SCLx remains low.
2
The BRG times out. The master attempts to release SCLx.
3
When the slave releases SCLx, the BRG restarts.
4
The BRG times out. The MSB of the response is shifted to the I2CxRSR register. SCLx is driven low for the next baud
5
At the falling edge of the eighth SCLx clock, the I2CxRSR register is transferred to the I2CxRCV register.
6
RCEN
(D) (Q) (Q)(D)(Q)
I2CxRCV
(Q)
1
Typically, the slave can pull SCLx low (clock stretch) to request a Wait to prepare the data response.
1
The slave will drive the MSB of the data response on SDAx when ready.
(Q)
interval.
The module clears the RCEN bit. The RBF status bit is set. Master generates the interrupt.
TBRG TBRG

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