Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 28 2014 Microchip Technology Inc.
Figure 3-8: SPIx Master/Framed Master Timing (FRMDLY = 0)
Figure 3-9: SPIx Master/Framed Master Timing (FRMDLY = 1)
SCKx
SSx
SDOx
(CKP = 0)
bit 14 bit 13 bit 12
SDIx
bit 14 bit 13 bit 12
Write to SPIxBUF
Receive Samples at SDIx
Pulse Generated at SSx
SCKx
(CKP = 1)
(FRMPOL = 1)
SSx
(FRMPOL = 0)
bit 15
bit 15
SCKx
SDOx
(CKP = 0)
bit 14 bit 13 bit 12
SDIx
bit 14 bit 13 bit 12
Write to SPIxBUF
Pulse Generated by SSx,
SCKx
(CKP = 1)
SSx
(FRMPOL = 1)
SSx
(FRMPOL = 0)
Receive Samples at SDIx
bit 15
bit 15

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