Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 16 2014 Microchip Technology Inc.
Figure 3-2: SPIx Master Mode Timing
SCKx
(CKP = 0,
SCKx
(CKP = 1,
SCKx
(CKP = 0,
SCKx
(CKP = 1,
Four Clock
Input Sample
Input Sample
SDIx
bit 7 bit 0
SDOx
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDIx
SPIxIF
(SMP = 1)
(2)
(SMP = 0)
(2)
(SMP = 1)
(2)
CKE = 1)
(1)
CKE = 0)
(1)
CKE = 1)
(1)
CKE = 0)
(1)
(SMP = 0)
(2)
User Writes
to SPIxBUF
SDOx
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
One Instruction Cycle Latency
to Set the SPIxIF Flag bit
SPIxSR Moved
into SPIxRXB
User Reads
SPIxBUF
(SPIxSTAT<0>)
SPITBF
SPIxTXB to SPIxSR
(3)
User Writes New Data
during Transmission
SPIRBF
Two modes
modes
(clock
output at
the SCKx
pin in
Master
mode)
available
for SMP
Control
bit
(4)
bit 0
Note 1: Four SPIx Clock modes are shown only to demonstrate the CKP (SPIxCON1<6>) and CKE (SPIxCON1<8>) bits’
functionality. Only one of the four modes can be chosen for the operation.
2: The SDIx pin and the input sample are shown for two different values of the SMP bit (SPIxCON1<9>) only for
demonstration. Only one of the two configurations of the SMP bit can be chosen during the operation.
3: If there are no pending transmissions, the data in the SPIxTXB register is transferred to the SPIxSR register as
soon as the user application writes to the SPIxBUF register.
4: Operation for 8-bit mode is shown. The operation for 16-bit mode is similar to 8-bit, except for the number of clock
pulses.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf