Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2010 Microchip Technology Inc. Preliminary DS39735A-page 47-13
Section 47. Motor Control PWM
Motor Control
PWM
47
Register 47-10: PxFLTBCON: Fault B Control Register
(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 R/W-x
(2)
R/W-x
(2)
R/W-x
(2)
FLTBM FBEN3 FBEN2 FBEN1
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as 0
bit 13-8 FBOV3H:FBOV1L: Fault Input B PWM Override Value bits
1 = PWM output pin is driven active on an external Fault input event
0 = PWM output pin is driven inactive on an external Fault input event
bit 7 FLTBM: Fault B Mode bit
1 = Fault B input pin functions in Cycle-by-Cycle mode
0 = Fault B input pin latches all control pins to the programmed states in PxFLTBCON<15:8>
bit 6-3 Unimplemented: Read as 0
bit 2 FBEN3: Fault Input B Enable bit
(2)
1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input B
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input B
bit 1 FBEN2: Fault Input B Enable bit
(2)
1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input B
0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input B
bit 0 FBEN1: Fault Input B Enable bit
(2)
1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input B
0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input B
Note 1: In devices where the PWMLOCK bit is present in the FOSCSEL Configuration register, this register can be
write-protected. If the PWMLOCK input signal is asserted (PWMLOCK = 1), the PxFLTBCON register is
writable only after the proper sequence is written to the PWMKEY register. If the PWMLOCK input signal is
deasserted (PWMLOCK = 0), the PxFLTBCON register is writable at all times. Refer to Section 47.14.4
Write-Protected Registers for further details about the unlock sequence.
2: In devices where the PWMLOCk bit is present in the FOSCSEL Configuration register, the Reset value for
this bits is 1. Refer to the specific device data sheet for further details.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section47-Motor_Control_PWM.pdf