Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2007 Microchip Technology Inc. Advance Information DS39699B-page 23-14
Section 23. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
23
Figure 23-6: SPIx Slave Mode Timing (Slave Select Pin Enabled)
(3)
SCKx
(CKP = 1
SCKx
(CKP = 0
Input
Sample
SDIx
bit 7
bit 0
SDOx
bit 7
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
SPIxIF
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
User writes
SPIxBUF
SPIxSR to
SPIxBUF
SSx
(1)
Note 1: When the SSEN (SPIxCON1<7>) bit is set to ‘1’, the SSx pin must be driven low so as to enable transmission and
reception in Slave mode.
2: Transmit data is held in SPIxTXB and SPIxTBF remains set until all bits are transmitted.
3: Operation for 8-bit mode shown; the 16-bit mode is similar.
User reads
SPIxBUF
SPIxRBF
1 instruction
cycle latency
SPIxTBF
(2)
SPIxBUF
to
SPIxSR
to
bit 0
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section23-Serial_Peripheral_Interface.pdf