Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2010 Microchip Technology Inc. Preliminary DS39735A-page 47-27
Section 47. Motor Control PWM
Motor Control
PWM
47
47.9.4 Complementary PWM Output Mode
Complementary PWM Output mode is used to drive inverter loads similar to the one shown in
Figure 47-8. This inverter topology is typical for ACIM and BLDC applications. In
Complementary PWM Output mode, a pair of PWM outputs cannot be active simultaneously.
Each PWM channel and output pin pair are internally configured as shown in Figure 47-9. A
dead time can be optionally inserted during device switching, making both outputs inactive for a
short period. (Refer to Section 47.14 Special Features of the MCPWM Module.)
Figure 47-8: Typical Load for Complementary PWM Outputs
Complementary PWM Output mode is selected for each PWM I/O pin pair by clearing the
appropriate PWM I/O Pair Mode (PMOD) bits in PWM Control Register 1 (PWMxCON1<11:8>).
The PWM I/O pins are set to Complementary PWM Output mode by default on a device Reset.
Figure 47-9: PWM Channel Block Diagram, Complementary PWM Output Mode
+V
1H
1L
3-Phase
Load
2H
2L
3H
3L
Dead-Time
Generator
PWM Generator
PWMxH3:
PWMxL3:
Override
and
Fault Logic
PWMxH1
PWMxL1

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