Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

2007-2014 Microchip Technology Inc. DS70000195F-page 33
Figure 5-12: Master Message (10-Bit Reception)
1
Setting the SEN bit starts a Start event.
AKDT
ACKEN
SEN
SCLx
SDAx
SCLx
SDAx
I2CxTRN
TBF
I2CxRCV
RBF
MI2CxIF
ACKSTAT
1 2 3 4 5 6 7 8
A9 A8
9
A
PEN
RCEN
1 2 3 4 5 6 7 8
D3 D2 D1 D0D7 D6 D5 D4
A7 A6 A5 A4 A3 A2 A1 A0
1 2 3 4 5 6 7 8 9
W01 1 1 1
RSEN
A9 A8
01 1 1 1 R
1 2 3 4 5 6 7 8 9
1 32
9
A
1 2 3 4 5 6 7
D3 D2 D1D7 D6 D5 D4
AA
4 5 6 7 8
2
Writing the I2CxTRN register starts a master transmission. The data is the first
3
Writing the I2CxTRN register starts a master transmission. The data is the second
4
Setting the RSEN bit starts a master Restart event.
5
Writing the I2CxTRN register starts a master transmission. The data is a re-send
6
Setting the RCEN bit starts a master reception. On interrupt
7
Setting the ACKEN bit starts an Acknowledge event. ACK
8
Setting the RCEN bit starts a master reception.
9
Setting the ACKEN bit starts an Acknowledge event. ACK
Setting the PEN bit starts a master Stop event.
byte of the address with the R/W
status bit cleared.
byte of the address.
of the first byte with the R/W
status bit set.
the I2CxRCV register, which clears the RBF status bit.
(Slave)
(Slave)
(Master)
(Master)
MI2CxIF Interrupt Flag Cleared in User Software
10

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh