Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2005-2011 Microchip Technology Inc. DS70157F-page 11
Section 2. Programmer’s Model
Programmer’s
Model
2
2.1.1.5 ARITHMETIC AND LOGIC UNIT
A high-speed, 17-bit by 17-bit multiplier is included to significantly enhance the core’s arithmetic
capability and throughput. The multiplier supports Signed, Unsigned, and Mixed modes, as well
as 16-bit by 16-bit, or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a
single cycle.
The 16-bit Arithmetic Logic Unit (ALU) is enhanced with integer divide assist hardware that
supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT
instruction looping mechanism, and a selection of iterative divide instructions, to support 32-bit
(or 16-bit) divided by 16-bit integer signed and unsigned division. All divide operations require 19
cycles to complete, but are interruptible at any cycle boundary.
2.1.1.6 EXCEPTION PROCESSING
The 16-bit MCU and DSC devices have a vectored exception scheme with support for up to 8
sources of non-maskable traps and up to 246 interrupt sources. In both families, each interrupt
source can be assigned to one of seven priority levels.
2.1.2 PIC24E and dsPIC33E Features
In addition to the information provided in Section 2.1.1 “Features Specific to 16-bit MCU and
DSC Core”, this section describes the enhancements that are available in the PIC24E and
dsPIC33E families of devices.
2.1.2.1 DATA SPACE ADDRESSING
The Base Data Space address is used in conjunction with a read or write page register (DSRPAG
or DSWPAG) to form an Extended Data Space (EDS) address, which can also be used for PSV
access. The EDS can be addressed as 8 M words or 16 Mbytes. Refer to Section 3. “Data
Memory” (DS70595) in the “dsPIC33E/PIC24E Family Reference Manual” for more details on
EDS, PSV, and table accesses.
2.1.2.2 AUTOMATIC MIXED-SIGN MULTIPLICATION MODE (dsPIC33E ONLY)
In addition to signed and unsigned DSP multiplications, dsPIC33E devices support mixed-sign
(unsigned-signed and signed-unsigned) multiplications without the need to dynamically
reconfigure the multiplication mode and shift data to account for the difference in operand
formats. This mode is particularly beneficial for executing extended-precision (32-bit and 64-bit)
algorithms. Besides DSP instructions, MCU multiplication (MUL) instructions can also utilize
either accumulator as a result destination, thereby enabling faster extended-precision arithmetic.
Refer to
4.10.1 “Implied DSP Operands (dsPIC30F, dsPIC33F and dsPIC33E Devices)” and
4.18 “Extended-precison Arithmetic using mixed-sign multiplications (dsPIC33E only)”
for more details on mixed-sign DSP multiplications.
2.1.2.3 MCU MULTIPLICATIONS WITH 16-BIT RESULT
16x16-bit MUL instructions include an option to store the product in a single 16-bit working
register rather than a pair of registers. This feature helps free up a register for other purposes, in
cases where the numbers being multiplied are small in magnitude and therefore expected to
provide a 16-bit result. See the individual MUL instruction descriptions in
5.4 “Instruction
Descriptions” for more details.
2.1.2.4 HARDWARE STACK FOR DO LOOPS (dsPIC33E ONLY)
The single-level DO loop shadow register-set has been replaced by 4-level deep DO loop
hardware stack. This provides automatic DO loop register save/restore for up to 3 levels of DO
loop nesting, resulting in more efficient implementation of nested loops. Refer to 2.19 “DO Stack
(dsPIC33E Devices)” for more details on DO loop nesting in dsPIC33E devices.
Note: Some PIC24F devices also support Extended Data Space. Refer to Section 44.
“CPU with EDS” (DS39732) and Section 45. “Data Memory with EDS”
(DS39733) of the PIC24F Family Reference Manual for details.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf