Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2007-2014 Microchip Technology Inc. DS70000195F-page 51
Inter-Integrated Circuit™ (I
2
C™)
7.4.4 EXAMPLE MESSAGES OF SLAVE RECEPTION
Receiving a slave message is an automatic process. The user software handling the slave
protocol uses the slave interrupt to synchronize to the events.
When the slave detects the valid address, the associated interrupt will notify the user software to
expect a message. On receive data, as each data byte transfers to the I2CxRCV register, an
interrupt notifies the user software to unload the buffer.
Figure 7-11 illustrates a simple receive message. Because it is a 7-bit address message, only
one interrupt occurs for the address bytes. Then, interrupts occur for each of four data bytes. At
an interrupt, the user software may monitor the status bits, RBF (I2CxSTAT<1>), D/A
(I2CxSTAT<5>) and R/W (IC2xSTAT<2>), to determine the condition of the byte received.
Figure 7-12 illustrates a similar message using a 10-bit address. In this case, two bytes are
required for the address.
Figure 7-13 illustrates a case where the user software does not respond to the received byte
and the buffer overruns. On reception of the second byte, the module will automatically NACK
the master transmission. Generally, this causes the master to re-send the previous byte. The
I2COV status bit (I2CxSTAT<6>) indicates that the buffer has overrun. The I2CxRCV register
buffer retains the contents of the first byte. On reception of the third byte, the buffer is still full,
and again, the module will NACK the master. After this, the user software finally reads the
buffer. Reading the buffer will clear the RBF status bit; however, the I2COV status bit remains
set. The user software must clear the I2COV status bit (I2CxSTAT<6>). The next received byte
is moved to the I2CxRCV register buffer and the module responds with an ACK
.
Figure 7-14 highlights clock stretching while receiving data. In the previous examples, the
STREN bit (I2CxCON<6> or I2CxCONL<6>) is equal to ‘0’, which disables clock stretching on
receive messages. In this example, the user software sets STREN to enable clock stretching.
When STREN = 1, the module will automatically clock stretch after each received data byte,
allowing the user software more time to move the data from the buffer. If RBF = 1 at the falling
edge of the ninth clock, the module automatically clears the SCLREL bit (I2CxCON<12> or
I2CxCONL<12>) and pulls the SCLx bus line low. As shown with the second received data
byte, if the user software can read the buffer and clear the RBF status bit before the falling
edge of the ninth clock, the clock stretching will not occur. The user software can also suspend
the bus at any time. By clearing the SCLREL bit, the module pulls the SCLx line low after it
detects the bus SCLx low. The SCLx line remains low, suspending transactions on the bus until
the SCLREL bit is set.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-PIC24FJ32MC102-I2C.pdf