Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

DS70000195F-page 60 2007-2014 Microchip Technology Inc.
Figure 7-17: I
2
C™ Slave, 7-Bit Address, Reception (STREN = 1, AHEN = 1, DHEN = 1)
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDAx
SCLx
SI2CxIF
RBF
ACKDT
SCLREL
1 2
3 4
5 6 7 8
9
1 2
3
4 5 6 7 8 9
1 2
3 4 5 6 7 8
ACKTIM
1 Detecting Start bit, enables address detection, interrupt is set if SCEN is set.
2
User software clears the interrupt flag.
3
Slave receives first address byte. Write Indicated. If AHEN = 1, SCLREL is cleared
4
User software clears the interrupt flag.
5
ACKDT is written with ACK by user software.
7
Hardware stretches the clock after ACK (if STREN =
8
User software sets SCLREL to release clock hold.
9 I2CxRCV is loaded with I2CxRSR. RBF is set. If DHE
User software sets SCLREL to release the clock hold.
User software reads I2CxRCV, that clears the RB
1 3 4 5 6
7
2 98
6
User software sets SCLREL to release the clock hold; ACKTIM is cleared by hardware.
by hardware. ACKTIM and interrupt are asserted.
cleared by hardware and ACKTIM is asserted.
by hardware. After Acknowledgment, hardware st
NACK sent by master.
Module recognizes the Stop event.
ACK ACK
10 11
10
11
12
13

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