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© 2005-2011 Microchip Technology Inc. DS70157F-page 201
Section 5. Instruction Descriptions
Instruction
Descriptions
5
CPB
Compare Ws with Wb using Borrow, Set Status Flags
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} CPB{.B} Wb, Ws
[Ws]
[Ws++]
[Ws--]
[++Ws]
[--Ws]
Operands: Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Operation: (Wb) – (Ws) – (C
)
Status Affected: DC, N, OV, Z, C
Encoding: 1110 0001 1www wB00 0ppp ssss
Description: Compute (Wb) – (Ws) – (C
), and update the STATUS register. This
instruction is equivalent to the SUBB instruction, but the result of the
subtraction is not stored. Register direct addressing must be used for Wb.
Register direct or indirect addressing may be used for Ws.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the address of the Ws source register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
CPB.B W0, [W1++] ; Compare [W1] with W0 using C (Byte mode)
; Post-increment W1
Before
Instruction
After
Instruction
W0 ABA9 W0 ABA9
W1 1000 W1 1001
Data 1000 D0A9 Data 1000 D0A9
SR 0002 (Z = 1) SR 0008 (N = 1)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf