Vault 7: Projects

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© 2010 Microchip Technology Inc. DS39719D-page 32-5
Section 32. High-Level Device Integration
High-Level Device
Integration
32
32.2.2 PIC24F K-Series Flash Devices
For PIC24F devices with K-series Flash memory, the Configuration bits are implemented as a
physically separate block of nonvolatile memory. Once programmed, configuration data is main-
tained indefinitely. Although they act like fuses, the Configuration bits are freely reprogrammable.
Since they lie inside the configuration memory space, the Configuration bits are not directly
accessible; they can only be written and read using table read and table write instructions.
Unlike the Flash Configuration Words in J-series devices, the Configuration bits in K-series
devices are organized into 8-bit registers, always the Least Significant Byte (LSB) of a program
memory address. These Configuration registers are symbolically named according to their
primary function (i.e., General Segment Protection, Oscillator Selection, etc.). Table 32-3 shows
the typical names and addresses of Configuration registers in K-series devices. Note that not all
Configuration registers are implemented on all devices, and certain devices with extended
feature sets, may have additional registers. In addition, there may be variations in naming or
location of registers in certain devices. Refer to the device data sheet for specific information.
Like J-series Flash devices, the Configuration bits can be programmed (read as 0), or left
unprogrammed (read as 1), to select various configuration options. Changes to Configuration
bits during programming take effect immediately and do not require a device Reset.
The implementation of the Configuration bits in K-series devices makes a Configuration
Mismatch (CM) error and Reset during full-speed operation virtually impossible. However, a
severe device disturbance (such as an ESD event) during Sleep or Deep Sleep may disrupt the
configuration safety check, resulting in a CM Reset.
Table 32-3: Typical PIC24F K-Series Configuration Registers
Register Name Primary Function Address
FBS Boot Segment Protect F80000h
FGS General Segment Protect F80004h
FOSCEL Oscillator Select F80006h
FOSC Oscillator Configure F80008h
FWDT Watchdog Timer Configure F8000Ah
FPOR Reset Configure F8000Ch
FICD Debug Configure F8000Eh
FDS Deep Sleep Configure F80010h

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