Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
PIC24F Family Reference Manual
DS39707A-page 8-10 Advance Information © 2006 Microchip Technology Inc.
8.3.2 Interrupt Latency for Two-Cycle Instructions
The interrupt latency during a two-cycle instruction is the same as during a one-cycle instruction.
The first and second cycle of the interrupt process allow the two-cycle instruction to complete
execution. The timing diagram in Figure 8-5 shows the case when the peripheral interrupt event
occurs in the instruction cycle prior to execution of the two-cycle instruction.
Figure 8-6 shows the timing when a peripheral interrupt is coincident with the first cycle of a
two-cycle instruction. In this case, the interrupt process completes as for a one-cycle instruction
(see Section 8.3.1 “Interrupt Latency for One-Cycle Instructions”).
Figure 8-4: Interrupt Timing During a Two-Cycle Instruction
Figure 8-5: Interrupt Timing, Interrupt Occurs During 1st Cycle of a 2-Cycle Instruction
4 6 6 64 4
INST(PC – 2)
INST(PC) INST(PC)
FNOP ISR
INST
Executed
Interrupt Flag
PUSH low 16 bits of PC
PUSH SRL and high 8 bits of PC
64
ISR + 2 ISR + 4
CPU Priority
Fetch
2000 (ISR) 2002 2004 2006PC PC + 2PC
Vector
Save PC in
Status bit
Vector#
Peripheral interrupt event
occurs at or before
TCY
1
2
3
4
2nd cycle1st Cycle
temporary
buffer.
midpoint of this cycle.
(from temporary buffer).
(from temporary buffer).
Note: Where FNOP is a forced NOP instruction automatically inserted by the CPU.
4 6 6 64 4
INST(PC) INST(PC)
FNOP ISR
INST
Executed
Interrupt Flag
PUSH low 16 bits of PC
PUSH SRL and high 8 bits of PC
64
ISR + 2 ISR + 4
CPU Priority
Fetch
2000 (ISR) 2002 2004 2006PC PC + 2PC
Vector
Save PC in
Status bit
Vector#
Peripheral interrupt event
occurs at or before
TCY
1
2
3
4
2nd cycle1st cycle
temporary
buffer.
FNOP
midpoint of this cycle.
(from temporary buffer).
(from temporary buffer).
Note: Where FNOP is a forced NOP instruction automatically inserted by the CPU.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section8-Interrupts.pdf