Vault 7: Projects

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© 2005-2011 Microchip Technology Inc. DS70157F-page 285
Section 5. Instruction Descriptions
Instruction
Descriptions
5
MOV
Move [Ws with offset] to Wnd
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} MOV{.B} [Ws + Slit10], Wnd
Operands: Ws [W0 ... W15]
Slit10 [-512 ... 511] for byte operation
Slit10 [-1024 ... 1022] (even only) for word operation
Wnd [W0 ... W15]
Operation: [Ws + Slit10] Wnd
Status Affected: None
Encoding:
1001 0kkk kBkk kddd dkkk ssss
Description: The contents of [Ws + Slit10] are loaded into Wnd. In Word mode, the
range of Slit10 is increased to [-1024 ... 1022] and Slit10 must be even to
maintain word address alignment. Register indirect addressing must be
used for the source, and direct addressing must be used for Wnd.
The ‘k’ bits specify the value of the literal.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘d’ bits select the destination register.
The ‘s’ bits select the source register.
Note 1: The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.
2: In Byte mode, the range of Slit10 is not reduced as specified in
Section 4.6 “Using 10-bit Literal Operands”, since the literal
represents an address offset from Ws.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
MOV.B [W8+0x13], W10 ; load W10 with [W8+0x13]
; (Byte mode)
Before
Instruction
After
Instruction
W8 1008 W8 1008
W10 4009 W10 4033
Data 101A 3312 Data 101A 3312
SR 0000 SR 0000

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