Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

PIC24F Family Reference Manual
DS39700C-page 6-18 © 2009 Microchip Technology Inc.
6.6 PHASE LOCK LOOP (PLL) BRANCH
The system clock for all PIC24F devices includes a frequency multiplier branch built around a
Phase Lock Loop (PLL). This branch allows the user to obtain a higher clock speed using a
low-speed Primary Oscillator or external clock source, eliminating the need for an expensive
high-speed crystal or resonator. It also allows the use of the Internal Fast RC Oscillator (FRC) to
clock the device at its maximum operating speed without the use of an external oscillator.
There are several different versions of the PLL block implemented on PIC24F devices; the
version implemented depends on the particular device family. Some PLL blocks provide a single
branch, frequency multiplied output. Others provide multiple branches with clocks at different fre-
quencies, including a special clock for a particular peripheral. Users should refer to the particular
device data sheet to see which PLL block is implemented.
6.6.1 Basic 4x PLL Block
In most PIC24F devices, the implemented PLL block is the basic PLL (Figure 6-7). This provides
a fixed 4x multiplier, which can be used with XT and EC Primary Oscillators and the FRC
Oscillator. The PLL accepts any frequency input from approximately 3.5 MHz to 8 MHz.
Whenever the clock source of the PLL is changed, the PLL ready timer must be reset to allow
the PLL to synchronize to the new clock source. After the ready timer has counted the required
time, the PLL output is ready for use.
Figure 6-7: Basic 4x PLL Block
4x PLL
Input from POSC
Input from FRC
4 MHz
8 MHz
HSPLL/ECPLL/FRCPLL Output
FNOSC<2:0>
011
001

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