Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2009-2013 Microchip Technology Inc. DS70000582E-page 23
UART
Figure 7-1: UARTx Receiver Block Diagram
URX8 UxRXREG Low Byte
Load UxRSR
UxMODE
Receive Buffer Control
Generate Flags
Generate Interrupt
UxRXIF
UxRX
Start bit Detect
Receive Shift Register
Control
Signals
16x Baud Clock
from Baud Rate
Generator
UxSTA
Shift Data Characters
to Buffer
9
(UxRSR)
PERR
FERR
Parity Check
Stop bit Detect
Shift Clock Generation
Wake Logic
16
Internal Data Bus
1
0
LPBACK
From UxTX
15 9 8 7 0
Word Word or
Byte Read
BCLKx/UxRTS
UxCTS
Selection
UEN
BCLKx
UEN1
UEN0
16 Divider
UxRTS
UxCTS
Note: The x denotes the UART number.
Read-Only
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Universal_Asynchronous_Receiver_Transmitter.pdf