Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

dsPIC33/PIC24 Family Reference Manual
DS70000195F-page 22 2007-2014 Microchip Technology Inc.
5.2 Sending Data to a Slave Device
The transmission of a data byte, a 7-bit device address byte or the second byte of a 10-bit
address, is accomplished by writing the appropriate value to the I2CxTRN register. Loading this
register will start the following process:
1. The user software loads the I2CxTRN register with the data byte to transmit.
2. Writing to the I2CxTRN register sets the TBF bit (I2CxSTAT<0>).
3. The data byte is shifted out through the SDAx pin until all 8 bits are transmitted. Each bit
of address or data will be shifted out onto the SDAx pin after the falling edge of SCLx.
4. On the ninth SCLx clock, the module shifts in the ACK
bit from the slave device and writes
its value into the ACKSTAT status bit (I2CxSTAT<15>).
5. The module generates the MI2CxIF interrupt at the end of the ninth SCLx clock cycle.
The module does not generate or validate the data bytes. The contents and usage of the bytes
are dependent on the state of the message protocol maintained by the user software.
The sequence of events that occur during master transmission and master reception are
provided in Figure 5-3.
Figure 5-3: Master Transmission Timing Diagram
D7 D6 D5 D4 D3 D2 D1 D0
SCLx (Master)
SCLx (Slave)
SDAx (Master)
SDAx (Slave)
TBF
I2CxTRN
MI2CxIF Interrupt
TBRG TBRG
5 6 7 81 2 3 4
Writing the I2CxTRN register will start a master transmission event. The TBF status bit is set.
1
The BRG starts. The Most Significant Byte (MSB) of the I2CxTRN register drives SDAx. The SCLx remains low.
2
The BRG times out. The SCLx is released and the BRG restarts.
3
The BRG times out. The SCLx is driven low. After SCLx is detected low, the next bit of the I2CxTRN register drives SDAx.
4
While the SCLx is low, the slave can also pull the SCLx low to initiate a Wait (clock stretch).
5
Master has already released SCLx and slave can release to end Wait. The BRG restarts.
6
At the falling edge of the eighth SCLx clock, the master releases SDAx. The TBF status bit is cleared.
7
At the falling edge of the ninth SCLx clock, the master generates the interrupt. The SCLx remains low until the next event.
8
The slave releases SDAx and the TRSTAT status bit is clear.
I
2
C™ Bus State
(Q) (D) (Q) (A) (Q)(D) (Q)
TRSTAT
ACKSTAT
The TRSTAT status bit is set.
The slave drives an ACK
/NACK.

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