Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 4 2014 Microchip Technology Inc.
Figure 1-2: SPIx Module Block Diagram – Enhanced Mode
Internal Data Bus
SDIx
SDOx
SSx
/FSYNCx
SCKx
bit 0
Shift Control
Edge
Select
F
P
Enable
Sync
Control
TransferTransfer
Write SPIxBUF
Read SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Primary
1:1/4/16/64
Prescaler
Secondary
Prescaler
1:1 to 1:8
8-Level FIFO
Receive Buffer
8-Level FIFO
Transmit Buffer
SPIxBUF
Clock
Control
SPIxSR
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf