Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

DS70000195F-page 66 2007-2014 Microchip Technology Inc.
13.0 REGISTER MAPS
A summary of the registers associated with the I
2
C module is provided in Table 13-1 and Table 13-2.
Table 13-1: I2Cx Register Map
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
I2CxRCV
I2Cx Receive Register
I2CxTRN
I2CxTransmit Register
I2CxBRG
I2Cx Baud Rate Generator Register
I2CxCON
(1)
I2CEN I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN
I2CxSTAT ACKSTAT TRSTAT ACKTIM
(1)
BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W
I2CxADD
I2Cx Address Register
I2CxMSK
I2Cx Address Mask
ISRCCON ISRCEN
OUTSEL2 OUTSEL1 OUTSEL0 ISRCCAL5 ISRCCAL4 ISRCCAL3 ISRCCAL2
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These registers and/or bits are not available on all devices. Refer to the specific device data sheet for availability.
Table 13-2: I2Cx Register Map
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
I2CxRCV
I2Cx Receive Register
I2CxTRN
I2Cx Transmit Register
I2CxBRG
I2Cx Baud Rate Generator Register
I2CxCONL
(1)
I2CEN I2CSIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN
I2CxCONH
(1)
PCIE SCIE BOEN SDAHT SBCDE
I2CxSTAT ACKSTAT TRSTAT ACKTIM
(1)
BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W
I2CxADD
I2Cx Address Register
I2CxMSK
I2Cx Address Mask
ISRCCON ISRCEN
OUTSEL2 OUTSEL1 OUTSEL0 ISRCCAL5 ISRCCAL4 ISRCCAL3 ISRCCAL2
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These registers and/or bits are not available on all devices. Refer to the specific device data sheet for availability.

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