Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

2007-2014 Microchip Technology Inc. DS70000195F-page 21
Inter-Integrated Circuit™ (I
2
C™)
5.1 Generating Start Bus Event
To initiate a Start event, the user software sets the SEN bit (I2CxCON<0> or I2CxCONL<0>).
Prior to setting the Start bit, the user software can check the P status bit (I2CxSTAT<4>) to ensure
that the bus is in an Idle state.
Figure 5-2 illustrates the timing of the Start condition.
Slave logic detects the Start condition, sets the S status bit (I2CxSTAT<3>) and clears the
P status bit (I2CxSTAT<4>)
The SEN bit is automatically cleared at completion of the Start condition
The MI2CxIF interrupt is generated at completion of the Start condition
After the Start condition, the SDAx line and SCLx lines are left low (Q state)
5.1.1 IWCOL STATUS FLAG
If the user software writes to the I2CxTRN register when a Start sequence is in progress, the
IWCOL status bit (I2CxSTAT<7>) is set and the contents of the transmit buffer are unchanged
(the write does not occur).
Figure 5-2: Master Start Timing Diagram
Note: As the queuing of events is not allowed, writing to the lower 5 bits of the I2CxCON
or I2CxCONL register is disabled until the Start condition is complete.
SCLx (Master)
SDAx (Master)
S
SEN
MI2CxIF Interrupt
TBRG
1 2 3 4
1
TBRG
2
3
4
I
2
C™ Bus State
(I) (Q)
P
(S)
Writing SEN = 1 initiates a master Start
event. BRG starts.
The BRG times out. Master module
drives SDAx low. The BRG restarts.
The slave detects the Start and sets
S = 1 and P = 0.
The BRG times out. The master
module drives SCLx low, generates an
interrupt and clears the SEN bit.

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh