Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
PIC24F Family Reference Manual
DS39699B-page 23-11 Advance Information © 2007 Microchip Technology Inc.
Figure 23-4: SPIx Master Mode Timing
SCKx
(CKP = 0
SCKx
(CKP = 1
SCKx
(CKP = 0
SCKx
(CKP = 1
4 Clock
modes
Input
Sample
Input
Sample
SDIx
bit 7
bit 0
SDOx
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDIx
SPIxIF
(SMP = 1)
(2)
(SMP = 0)
(2)
(SMP = 1)
(2)
CKE = 1)
(1)
CKE = 0)
(1)
CKE = 1 )
(1)
CKE = 0)
(1)
(SMP = 0)
(2)
User writes
to SPIxBUF
SDOx
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
1 instruction cycle latency to set
SPIxIF flag bit
Note 1: Four SPIx Clock modes shown to demonstrate CKP (SPIxCON1<6>) and CKE (SPIxCON1<8>) bit functionality only.
Only one of the four modes can be chosen for operation.
2: SDIx and input sample shown for two different values of the SMP (SPIxCON1<9>) bit, for demonstration purposes
only. Only one of the two configurations of the SMP bit can be chosen during operation.
3: If there are no pending transmissions, SPIxTXB is transferred to SPIxSR as soon as the user writes to SPIxBUF.
4: Operation for 8-bit mode shown; the 16-bit mode is similar.
SPIxSR moved
into SPIxRXB
User reads
SPIxBUF
(clock
output at
the SCKx
pin in
Master
mode)
(SPIxSTAT<0>)
SPIxTBF
SPIxTXB to SPIxSR
(3)
User writes new data
during transmission
SPIxRBF
Two modes
available
for SMP
control
bit
(4)
bit 0
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section23-Serial_Peripheral_Interface.pdf