Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
PIC24F Family Reference Manual
DS39700C-page 6-8 © 2009 Microchip Technology Inc.
Register 6-2: CLKDIV: Clock Divider Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
ROI DOZE2 DOZE1 DOZE0 DOZEN
(1)
RCDIV2 RCDIV1 RCDIV0
bit 15 bit 8
R/W-0 R/W-0
R/W-0 R/W-0 U-0 U-0 U-0 U-0
CPDIV1
(2)
CPDIV0
(2)
PLLEN
(2)
G1CLKSEL
(2)
— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROI: Recover on Interrupt bit
1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: CPU Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 11 DOZEN: DOZE Enable bit
(1)
1 = When the DOZE<2:0> bits specify the CPU peripheral clock ratio
0 = The CPU peripheral clock ratio set to 1:1
bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits
111 = 31.25 kHz (divide-by-256)
110 = 125 kHz (divide-by-64)
101 = 250 kHz (divide-by-32)
100 = 500 kHz (divide-by-16)
011 = 1 MHz (divide-by-8)
010 = 2 MHz (divide-by-4)
001 = 4 MHz (divide by 2)
000 = 8 MHz (divide by 1)
bit 7-6 CPDIV<1:0>: System Clock Select bits
(2)
11 = 4 MHz (divide-by-8)
(3)
10 = 8 MHz (divide-by-4)
(3)
01 = 16 MHz (divide-by-2)
00 = 32 MHz (divide-by-1)
bit 5 PLLEN: 96 MHz PLL Enable bit
(2)
The 96 MHz PLL must be enabled when the USB or the graphics controller module is enabled; This con-
trol bit can be overridden by Configuration bits in some PIC24F devices. Refer to Section 6.6.2 “96 MHz
PLL Block” for details.
1 = Enable the 96 MHz PLL for USB and/or graphics controller operation
0 = Disable the 96 MHz PLL
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
2: These bits are available on USB-enabled or graphics-enabled devices only.
3: These system clock options are not compatible with the operation of the USB module. They may be used in
those instances when the PLL branch is selected as a clock source and the USB module is disabled.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section6-Oscillator.pdf