Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
dsPIC33/PIC24 Family Reference Manual
DS70005185A-page 20 2014 Microchip Technology Inc.
Figure 3-4: SPIx Slave Mode Timing (Slave Select Pin Enabled)
(
3
)
SCKx
SCKx
Input
SDIx
bit 7
bit 0
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
SPIxIF
User Writes
SPIxSR to
SPIxBUF
SSx
(1)
Note 1: When the SSEN bit is set (SPIxCON1<7> = 1), the SSx pin must be driven low to enable transmission and
reception in Slave mode.
2: Transmit data is held in the SPIxTXB register and the SPITBF bit remains set until all bits are transmitted.
3: Operation for 8-bit mode is shown; the operation for 16-bit mode is similar.
User Reads
SPIxBUF
SPIRBF
One Instruction
Cycle Latency
SPITBF
(2)
SPIxBUF
to
SPIxSR
to SPIxBUF
bit 0
(CKP = 0,
CKE = 0)
(CKP = 1,
CKE = 0)
(SMP = 0)
Sample
(SMP = 0)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf