Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2007-2014 Microchip Technology Inc. DS70000195F-page 45
Figure 7-8: I
2
C™ Slave, 10-Bit Address, Reception (STREN = 0, AHEN = 1, DHEN = 0)
1 1 1 1 0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1
SDAx
SCLx
SI2CxIF
RBF
ACKDT
ADD10
SCLREL
ACKTIM
1 2 3 4 5 6 7 8
9
ACK
ACK
1 2
3 4 5 6 7 8
9
1 2 3 4 5 6 7
1
Detecting the Start bit enables address detection; interrupt is set if the SCEN bit is set.
2
User software clears the interrupt flag.
3
Slave receives first address byte. Write indicated. Interrupt flag is asserted. ACKTIM
4
User software clears the interrupt flag.
5
ACKDT is written with ACK
by user software.
6
User software sets SCLREL to release clock hol
7
Slave interrupt is asserted.
8 User software reads I2CxRCV buffer, that clears RBF
9 Slave Acknowledges the second address byt
10
User software reads data from the I2CxRCV
is asserted. If AHEN = 1, slave suspends clock. SCLREL is cleared by hardware.
1 3
4
5
6
7 8
9
2
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-PIC24FJ32MC102-I2C.pdf