Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
dsPIC33/PIC24 Family Reference Manual
DS70000582E-page 46 2009-2013 Microchip Technology Inc.
Register 15-2: UxSCINT: UARTx Smart Card Interrupt Register
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
RXRPTIF
(1)
TXRPTIF
(1)
WTCIF GTCIF
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
PARIE RXRPTIE TXRPTIE WTCIE GTCIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as 0
bit 13 RXRPTIF: Receive Repeat Interrupt Flag bit
(1)
1 = Parity error has persisted after the same character has been received five times (four retransmits)
0 = Flag is cleared
bit 12 TXRPTIF: Transmit Repeat Interrupt Flag bit
(1)
1 = Line error has been detected after the last retransmit per TXRPT<1:0> (see Register 15-1)
0 = Flag is cleared
bit 11-10 Unimplemented: Read as 0
bit 9 PTRCL: Smart Card Protocol Selection bit
1 = T = 1
0 = T = 0
bit 8 SCEN: Smart Card Mode Enable bit
1 = Smart Card mode is enabled if UARTEN (UxMODE<15>) = 1
0 = Smart Card mode disabled
bit 7 Unimplemented: Read as 0
bit 6 PARIE: Parity Interrupt Enable bit
1 = An interrupt is invoked when a character is received with a parity error; see the PERR bit
(UxSTA<3>) in Register 2-2 for the interrupt flag
0 = Interrupt is disabled
bit 5 RXRPTIE: Receive Repeat Interrupt Enable bit
1 = An interrupt is invoked when a parity error has persisted after the same character has been
received five times (four retransmits)
0 = Interrupt is disabled
bit 4 TXRPTIE: Transmit Repeat Interrupt Enable bit
1 = An interrupt is invoked when line error is detected after the last retransmit, per the TXRPT<1:0>
bits, has been completed (see Register 15-1)
0 = Interrupt is disabled
bit 3-2 Unimplemented: Read as 0
bit 1 WTCIE: Waiting Time Counter Interrupt Enable bit
1 = Waiting Time Counter interrupt is enabled
0 = Waiting Time Counter interrupt is disabled
bit 0 GTCIE: Guard Time Counter Interrupt Enable bit
1 = Guard Time Counter interrupt is enabled
0 = Guard Time Counter interrupt is disabled
Note 1: These bits are applicable to T = 0 only. See the PTRCL bit (UxSCCON<1>.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Universal_Asynchronous_Receiver_Transmitter.pdf