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© 2010 Microchip Technology Inc. Preliminary DS39737A-page 49-9
Section 49. 10-Bit ADC with 4 Simultaneous Conversions
10-Bit ADC with
4 Simultaneous
Conversions
49
Register 49-5: ADxCHS0: ADCx Input Channel 0 Select Register
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB
CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA
CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit
Same definition as bit 7.
bit 14-13 Unimplemented: Read as ‘0
bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
Same definition as bit<4:0>.
bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is AVss
bit 6-5 Unimplemented: Read as ‘0
bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits
(1)
00101 = Channel 0 positive input is AN5
00100 = Channel 0 positive input is AN4
00011 = Channel 0 positive input is AN3
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
Note 1: These bits have no effect when the CSCNA bit (ADxCON2<10>) = 1.

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