Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 76 © 2005-2011 Microchip Technology Inc.
4.8 CONDITIONAL BRANCH INSTRUCTIONS
Conditional branch instructions are used to direct program flow, based on the contents of the
STATUS register. These instructions are generally used in conjunction with a Compare class
instruction, but they may be employed effectively after any operation that modifies the STATUS
register.
The compare instructions CP, CP0 and CPB, perform a subtract operation
(minuend – subtrahend), but do not actually store the result of the subtraction. Instead, compare
instructions just update the flags in the STATUS register, such that an ensuing conditional branch
instruction may change program flow by testing the contents of the updated STATUS register. If
the result of the STATUS register test is true, the branch is taken. If the result of the STATUS
register test is false, the branch is not taken.
The conditional branch instructions supported by the dsPIC30F, dsPIC33F, and dsPIC33E
devices are shown in Table 4-8. This table identifies the condition in the STATUS register which
must be true for the branch to be taken. In some cases, just a single bit is tested (as in BRA C),
while in other cases, a complex logic operation is performed (as in BRA GT). For dsPIC30F,
dsPIC33F, and dsPIC33E devices, it is worth noting that both signed and unsigned conditional
tests are supported, and that support is provided for DSP algorithms with the OA, OB, SA and
SB condition mnemonics.
Table 4-8: Conditional Branch Instructions
Note 1: Instructions are of the form: BRA mnemonic, Expr.
2: GEU is identical to C and will reverse assemble to BRA C, Expr.
3: LTU is identical to NC and will reverse assemble to BRA NC, Expr.
4: This condition is only available in dsPIC30F, dsPIC33F, and dsPIC33E devices.
Condition
Mnemonic
(1)
Description Status Test
C Carry (not Borrow) C
GE Signed greater than or equal (N&&OV) || (N&&OV)
GEU
(2)
Unsigned greater than or equal C
GT Signed greater than (Z&&N&&OV) || (Z&&N&&OV)
GTU Unsigned greater than C&&Z
LE Signed less than or equal Z || (N&&OV) || (N&&OV)
LEU Unsigned less than or equal C || Z
LT Signed less than (N&&OV) || (N&&OV)
LTU
(3)
Unsigned less than C
N Negative N
NC Not Carry (Borrow) C
NN Not Negative N
NOV Not Overflow OV
NZ Not Zero Z
OA
(4)
Accumulator A overflow OA
OB
(4)
Accumulator B overflow OB
OV Overflow OV
SA
(4)
Accumulator A saturate SA
SB
(4)
Accumulator B saturate SB
Z Zero Z
Note: The “Compare and Skip” instructions (CPBEQ, CPBGT, CPBLT, CPBNE, CPSEQ,
CPSGT, CPSLT, and CPSNE) do not modify the STATUS register.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf