Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2014 Microchip Technology Inc. DS70005185A-page 33
Serial Peripheral Interface (SPI) Module
5.0 SPI OPERATION WITH DMA
The DMA module transfers data between the CPU and SPIx module without CPU assistance.
Refer to the specific device data sheet for the availability of the “Direct Memory Access (DMA)”
chapter for the particular device. When using the SPIx module with DMA, the SPIBEN bit can be
programmed to ‘0’, thereby disabling FIFO operation. For more information on the DMA module,
refer to the DMA Family Reference Manual section specific to the device.
If the DMA channel is associated with the SPIx receiver, the SPIx issues a DMA request every time
the data is ready to be moved from the SPIx module to RAM. The DMA transfers data from the
SPIxBUF register into RAM and issues a CPU interrupt after a predefined number of transfers.
Similarly, if the DMA channel is associated with the SPIx transmitter, the SPIx module issues a
DMA request after each successful transmission. After each DMA request, the DMA transfers
new data into the SPIxBUF register and issues a CPU interrupt after a predefined number of
transfers. Since the DMA channels are unidirectional, two DMA channels are required if the SPIx
module is used for both receive and transmit.
Starting a DMA transfer to and from the SPIx peripheral depends on the SPIx data direction and
whether the operation occurs in Slave or Master mode.
• TX Only in Master mode:
In this configuration, no DMA request is issued until the first block of SPIx data is sent. To
initiate the DMA transfers, the user application must first send data using the DMA Manual
Transfer mode or it must first write data into the SPIx Buffer (SPIxBUF), independently of the
DMA.
• RX Only in Master mode:
In this configuration, no DMA request is issued until the first block of SPIx data is received.
However, in Master mode, no data is received until the SPIx transmits first. To initiate the DMA
transfers, the user application must use DMA Null Data Write mode and start DMA Manual
Transfer mode.
• RX and TX in Master mode:
In this configuration, no DMA request is issued until the first block of SPIx data is received.
However, in Master mode, no data is received until the SPIx transmits. To initiate the DMA
transfers, the user application must first send data using the DMA Manual Transfer mode or it
must first write data into the SPIx Buffer (SPIxBUF), independently of the DMA.
• TX Only in Slave mode:
In this configuration, no DMA request is issued until the first block of SPIx data is received. To
initiate the DMA transfers, the user application must first send data using the DMA Manual
Transfer mode or it must first write data into the SPIx Buffer (SPIxBUF), independently of the
DMA.
• RX Only in Slave mode:
This configuration generates a DMA request as soon as the first SPIx data has arrived. Special
steps are not required by the user application to initiate the DMA transfer.
• RX and TX in Slave mode
In this configuration, no DMA request is issued until the first SPIx data block is received. To
initiate the DMA transfers, the user application must first send data using the DMA Manual
Transfer mode or it must first write data into the SPIx Buffer (SPIxBUF), independently of the
DMA.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf