Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2006 Microchip Technology Inc. Advance Information DS39707A-page 8-5
Section 8. Interrupts
Interrupts
8
8.2 NON-MASKABLE TRAPS
Traps can be considered as non-maskable, nestable interrupts which adhere to a fixed priority
structure. Traps are intended to provide the user a means to correct erroneous operation during
debug and when operating within the application. If the user does not intend to take corrective
action in the event of a trap error condition, these vectors must be loaded with the address of a
software routine that will reset the device. Otherwise, the trap vector is programmed with the
address of a service routine that will correct the trap condition.
The PIC24F has four implemented sources of non-maskable traps:
• Oscillator Failure Trap
• Stack Error Trap
• Address Error Trap
• Arithmetic Error Trap
The instruction that caused the trap is allowed to complete before exception processing begins.
Therefore, the user may have to correct the action of the instruction that caused the trap.
Each trap source has a fixed priority as defined by its position in the IVT. An oscillator failure trap
has the highest priority, while an arithmetic error trap has the lowest priority (see Figure 8-1). In
addition, trap sources are classified into two distinct categories: ‘Hard’ traps and ‘Soft’ traps.
8.2.1 Soft Traps
The arithmetic error trap (priority level 11) and stack error trap (priority level 12) are categorized
as ‘soft’ trap sources. Soft traps can be treated like non-maskable sources of interrupt that
adhere to the priority assigned by their position in the IVT. Soft traps are processed like interrupts
and require 2 cycles to be sampled and Acknowledged prior to exception processing. Therefore,
additional instructions may be executed before a soft trap is Acknowledged.
8.2.1.1 STACK ERROR TRAP (SOFT TRAP, LEVEL 12)
The stack is initialized to 0x0800 during Reset. A stack error trap will be generated should the
Stack Pointer address ever be less than 0x0800.
There is a Stack Limit register (SPLIM) associated with the Stack Pointer that is uninitialized at
Reset. The stack overflow check is not enabled until a word write to SPLIM occurs.
All Effective Addresses (EA) generated using W15 as a source or destination pointer are
compared against the value in SPLIM. Should the EA be greater than the contents of the SPLIM
register, then a stack error trap is generated. In addition, a stack error trap will be generated
should the EA calculation wrap over the end of data space (0xFFFF).
A stack error can be detected in software by polling the STKERR status bit (INTCON1<2>). To
avoid re-entering the Trap Service Routine, the STKERR status flag must be cleared in software
prior to returning from the trap with a RETFIE instruction.
8.2.1.2 MATH ERROR TRAP (LEVEL 11)
The Math Error trap will execute should an attempt be made to divide by zero. The math error
trap can be detected in software by polling the MATHERR status bit (INTCON1<4>). To avoid
re-entering the Trap Service Routine, the MATHERR status flag must be cleared in software prior
to returning from the trap with a RETFIE instruction.
8.2.2 Hard Traps
Hard traps include exceptions of priority level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into this category.
Like soft traps, hard traps can also be viewed as non-maskable sources of interrupt. The
difference between hard traps and soft traps is that hard traps force the CPU to stop code
execution after the instruction causing the trap has completed. Normal program execution flow
will not resume until after the trap has been Acknowledged and processed.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section8-Interrupts.pdf