Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
2014 Microchip Technology Inc. DS70005185A-page 19
Serial Peripheral Interface (SPI) Module
Figure 3-3: SPIx Slave Mode Timing (Slave Select Pin Disabled)
(3)
SCKx Input
SCKx Input
Input
SDIx Input
bit 7
bit 0
SDOx
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPIxIF
User Writes to
SPIxBUF
(2)
SPIxSR to
SPIxRXB
SPITBF
SPIRBF
Note 1: Two SPIx Clock modes are shown only to demonstrate the CKP (SPIxCON<6>) and CKE (SPIxCON<8>) bits’
functionality. Any combination of the CKP and CKE bits can be chosen for the module operation.
2: If there are no pending transmissions, or a transmission is in progress, the data in the SPIxBUF register is
transferred to the SPIxSR register as soon as the user application writes to the SPIxBUF register.
3: Operation for 8-bit mode is shown; the operation for 16-bit mode is similar.
One Instruction Cycle Latency
to Set the SPIxIF Flag bit
(CKP = 0,
CKE = 0)
(1)
(CKP = 1,
CKE = 0)
(1)
Output
(SMP = 0)
Sample
(SMP = 0)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Serial_Peripheral_Interface.pdf