Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
PIC24F Family Reference Manual
DS39698A-page 10-4 Advance Information © 2006 Microchip Technology Inc.
10.3.1.3 WAKE-UP FROM SLEEP MODE WITH CRYSTAL OSCILLATOR OR PLL
If the system clock source is derived from a crystal oscillator and/or the PLL, the Oscillator
Start-up Timer (OST) and/or PLL lock times must be applied before the system clock source is
made available to the device. As an exception to this rule, no oscillator delays are necessary if
the system clock source is the secondary oscillator and it was running while in Sleep mode. Note
that in spite of the T
VREG (if the regulator is enabled) and other delays applied, the crystal
oscillator (and PLL) may not be up and running.
10.3.1.4 FSCM DELAY AND SLEEP MODE
When waking from Sleep, a nominal 100 μs delay (TFSCM) is applied (after TVREG, if the regulator
is enabled) if both of the following are true:
• The oscillator was shut down while in Sleep mode
• The system clock is derived from a crystal oscillator source and/or the PLL
In most cases, the FSCM delay provides time for the OST to expire and the PLL to stabilize
before device execution resumes. If the FSCM is enabled, it will begin to monitor the system
clock source after the FSCM delay expires.
10.3.1.5 SLOW OSCILLATOR START-UP
The OST and PLL lock times may not have expired when the power-up delays have expired.
If the FSCM is enabled, then the device will detect this condition as a clock failure and a clock
fail trap will occur. The device will switch to the FRC oscillator and the user can re-enable the
crystal oscillator source in the clock failure Trap Service Routine.
If FSCM is NOT enabled, the device will not start executing code until the clock is stable. From
the user’s perspective, the device will appear to be in Sleep until the oscillator clock has started.
10.3.1.6 WAKE-UP FROM SLEEP ON INTERRUPT
User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Sleep
mode because the interrupt source is effectively disabled. To use an interrupt as a wake-up
source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater.
Any source of interrupt that is individually enabled, using its corresponding IE control bit in the
IECx registers, can wake-up the processor from Sleep mode. When the device wakes from Sleep
mode, one of two actions may occur:
• If the assigned priority for the interrupt is less than or equal to the current CPU priority, the
device will wake-up and continue code execution from the instruction following the PWRSAV
instruction that initiated Sleep mode.
• If the assigned priority level for the interrupt source is greater than the current CPU priority,
the device will wake-up and the CPU exception process will begin. Code execution will
continue from the first instruction of the ISR.
The SLEEP status bit (RCON<3>) is set upon wake-up.
10.3.1.7 WAKE-UP FROM SLEEP ON RESET
All sources of device Reset will wake the processor from Sleep mode. Any source of Reset (other
than a POR) that wakes the processor will set the SLEEP status bit (RCON<3>) to indicate that
the device was previously in Sleep mode.
On a Power-on Reset, the SLEEP bit is cleared.
10.3.1.8 WAKE-UP FROM SLEEP ON WATCHDOG TIME-OUT
If the Watchdog Timer (WDT) is enabled and expires while the device is in Sleep mode, the
processor will wake-up. The WDTO and SLEEP status bits (RCON<4:3>) are both set to indicate
that the device resumed operation due to the WDT expiration. Note that this event does not reset
the device. Operation continues from the instruction following the PWRSAV instruction that
initiated Sleep mode.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ32MC10X-Reference_Manual-Section10-Power-Saving_Features.pdf