Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2005-2011 Microchip Technology Inc. DS70157F-page 75
Section 4. Instruction Set Details
Instruction Set
Details
4
4.7.4 Stack Pointer Underflow
The stack is initialized to 0x0800 during Reset (0x1000 for PIC24E and dsPIC33E devices). A
stack error trap will be initiated should the Stack Pointer address ever be less than 0x0800
(0x1000 for PIC24E and dsPIC33E devices).
4.7.5 Stack Frame Active (SFA) Control (dsPIC33E and PIC24E
Devices)
W15 is never subject to paging and is therefore restricted to address range 0x000000 to
0x00FFFF. However, the Stack Frame Pointer (W14) for any user software function is only
dedicated to that function when a stack frame addressed by W14 is active (i.e., after a LNK
instruction). Therefore, it is desirable to have the ability to dynamically switch W14 between use
as a general purpose W register, and use as a Stack Frame Pointer. The SFA Status bit
(CORCON<2>) achieves this function without additional software overhead.
When the SFA bit is clear, W14 may be used with any page register. When SFA is set, W14 is
not subject to paging and is locked into the same address range as W15 (0x000000 to
0x00FFFF). Operation of the SFA register lock is as follows:
• The LNK instruction sets SFA (and creates a stack frame)
• The ULNK instruction clears SFA (and deletes the stack frame)
• The CALL, CALL.L, and RCALL instructions also stack the SFA bit (placing it in the LSb of
the stacked PC), and clear the SFA bit after the stacking operation is complete. The called
procedure is now free to either use W14 as a general purpose register, or create another
stack frame using the LNK instruction.
• The RETURN, RETLW and RETFIE instructions all restore the SFA bit from its previously
stacked value
The SFA bit is a read-only bit. It can only be set by execution of the LNK instruction, and cleared
by the ULNK, CALL, CALL.L, and RCALL instructions.
Note: Locations in data space between 0x0000 and 0x07FF (0x0FFF for PIC24E and
dsPIC33E devices) are, in general, reserved for core and peripheral Special
Function Registers (SFRs).
Note: In dsPIC33E and PIC24E devices, the SFA bit is stacked instead of PC<0>.
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf