Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

© 2010 Microchip Technology Inc. Preliminary DS39735A-page 47-31
Section 47. Motor Control PWM
Motor Control
PWM
47
47.11 PWM DUTY CYCLE RESOLUTION
In the MCPWM module, the effective resolution for the generated PWM pulses is a function of
the PWM frequency (or period) and the device operating frequency.
The maximum resolution (in bits) for a selected device oscillator and PWM frequency can be
determined using the following formula:
Equation 47-3: PWM Resolution
In Equation 47-3, F
PWM is the PWM switching frequency and FCY
is the device operating
frequency.
Table 47-1 shows the PWM resolutions and frequencies for a selection of execution speeds and
PxTPER values. The PWM frequencies in Table 47-1 are for Edge-Aligned (Free-Running
PxTMR) PWM mode. For Center-Aligned modes (Up/Down PxTMR mode), the PWM
frequencies are half the values in Table 47-1, as indicated in Table 47-2.
Table 47-1: Example of PWM Frequencies and Resolutions, 1:1 Prescaler,
Edge-Aligned PWM
T
CY (FCY) PxTPER Value
PxDC3:PxDC1
Value for 100%
PWM
Resolution
PWM Frequency
(F
PWM)
62.5 ns (16 MHz) 0x7FFE 0xFFFE 16 bits 488 kHz
62.5 ns (16 MHz) 0x3FE 0x7FE 11 bits 15.62 kHz
100 ns (10 MHz) 0x7FFE 0xFFFE 16 bits 305 Hz
100 ns (10 MHz) 0x1FE 0x3FE 10 bits 19.53 kHz
125 ns (8 MHz) 0x7FFE 0xFFFE 16 bits 244 Hz
125 ns (8 MHz) 0xFE 0x1FE 9 bits 31.25 kHz
250 ns (4 MHz) 0x7FFE 0xFFFE 16 bits 122 Hz
250 ns (4 MHz) 0x7E 0xFE 8 bits 31.25 kHz
Table 47-2: Example of PWM Frequencies and Resolutions, 1:1 Prescaler,
Center-Aligned PWM
T
CY (FCY) PxTPER Value
PxDC3:PxDC1
Value for 100%
PWM
Resolution
PWM Frequency
62.5 ns (16 MHz) 0x7FFE 0xFFFE 16 bits 244 Hz
62.5 ns (16 MHz) 0x3FFE 0x7FFE 15 bits 976 Hz
100 ns (10 MHz) 0x7FFE 0xFFFE 16 bits 152 Hz
100 ns (10 MHz) 0x1FFE 0x3FFE 14 bits 610 Hz
125 ns (8 MHz) 0x7FFE 0xFFFE 16 bits 122 Hz
125 ns (8 MHz) 0xFFE 0x1F FE 13 bits 976 Hz
250 ns (4 MHz) 0x7FFE 0xFFFE 16 bits 61 Hz
250 ns (4 MHz) 0x7FE 0xFFE 12 bits 976 Hz
Note: 100% duty cycle cannot be accomplished when PTPER = 0x7FFF. Maximum duty
cycle in this scenario is 100 percent minus one-half T
CY.
PWMResolution
2
2F
CY
FPWM
---------------
log=

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh