Vault 7: Projects
This publication series is about specific projects related to the Vault 7 main publication.
© 2005-2011 Microchip Technology Inc. DS70157F-page 225
Section 5. Instruction Descriptions
Instruction
Descriptions
5
Note 1: The extension .D in the instruction denotes a double word
(32-bit) dividend rather than a word dividend. You may use a
.W extension to denote a word operation, but it is not required.
2: Unexpected results will occur if the quotient can not be
represented in 16 bits. When this occurs for the double
operation (DIV.SD), the OV Status bit will be set and the
quotient and remainder should not be used. For the word
operation (DIV.S), only one type of overflow may occur
(0x8000/0xFFFF = + 32768 or 0x00008000), which allows the
OV Status bit to interpret the result.
3: Dividing by zero will initiate an arithmetic error trap during the
first cycle of execution.
4: This instruction is interruptible on each instruction cycle
boundary.
Words: 1
Cycles: 18 (plus 1 for REPEAT execution)
Example 1:
REPEAT #17 ; Execute DIV.S 18 times
DIV.S W3, W4 ; Divide W3 by W4
; Store quotient to W0, remainder to W1
Before
Instruction
After
Instruction
W0 5555 W0 013B
W1 1234 W1 0003
W3 3000 W3 3000
W4 0027 W4 0027
SR 0000 SR 0000
Example 2:
REPEAT #17 ; Execute DIV.SD 18 times
DIV.SD W0, W12 ; Divide W1:W0 by W12
; Store quotient to W0, remainder to W1
Before
Instruction
After
Instruction
W0 2500 W0 FA6B
W1 FF42 W1 EF00
W12 2200 W12 2200
SR 0000 SR 0008 (N = 1)
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