Vault 7: Projects
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16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 422 © 2005-2011 Microchip Technology Inc.
SUBR
Subtract f from WREG
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X X X X
Syntax: {label:} SUBR{.B} f {,WREG}
Operands: f ∈ [0 ... 8191]
Operation: (WREG) – (f) → destination designated by D
Status Affected: DC, N, OV, Z, C
Encoding: 1011 1101 0BDf ffff ffff ffff
Description: Subtract the contents of the specified file register from the contents of
the default working register WREG, and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG.
If WREG is not specified, the result is stored in the file register
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
Words: 1
Cycles:
1
(1)
Note 1:
In dsPIC33E and PIC24E devices, the listed cycle count does not apply to read and
read-modify-write operations on non-CPU Special Function Registers. For more
details, see
Note 3
in
Section 3.2.1 “Multi-Cycle Instructions”
.
Example 1:
SUBR.B 0x1FFF ; Sub. (0x1FFF) from WREG (Byte mode)
; Store result to 0x1FFF
Before
Instruction
After
Instruction
WREG (W0) 7804 WREG (W0) 7804
Data 1FFE 9439 Data 1FFE 7039
SR 0000 SR 0000
Example 2:
SUBR 0xA04, WREG ; Sub. (0xA04) from WREG (Word mode)
; Store result to WREG
Before
Instruction
After
Instruction
WREG (W0) 6234 WREG (W0) FFFF
Data 0A04 6235 Data 0A04 6235
SR 0000 SR 0008 (N = 1)
Protego_Release_01_05-Related-OEM-Documentation-PIC24FJ64GA004-Programmers_Reference_Manual.pdf