Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

2007-2014 Microchip Technology Inc. DS70000195F-page 69
Inter-Integrated Circuit™ (I
2
C™)
16.0 REVISION HISTORY
Revision A (February 2007)
This is the initial released version of this document.
Revision B (August 2008)
This revision includes the following corrections and updates:
Updated bit definitions for the ACKSTAT bit (I2CxSTAT<15>) and the D/A
bit
(I2CxSTAT<5>) in Register 3-4.
Updated the I2CBRG denominator from 1,111,111 to 10,000,000 in Equation 4-1.
Updated the I
2
C clock rate values in Table , removed the table notes and added a general
note just after the table.
Updated the last two paragraphs in Section 3.0 “Control and Status Registers” to clarify
the shift of matching address bytes in the I2CxRSR register to the I2CxRCV register.
Updated Section “” to clarify that the master function is enabled when the SEN bit is set,
and when data is loaded into the I2CxTRN register.
Several sections were updated to clarify NACK status in Slave mode. The affected sections
are:
- Section 4.2 “I
2
C Interrupts”
- Section 7.5 “Sending Data to a Master Device”
- Figure 7-13 through Figure 7-16
The IPMIEN bit was incorrectly described as the Intelligent Peripheral Management
Interface Enable bit. All occurrences have been updated to Intelligent Platform
Management Interface bit.
Updated Section 9.2 “Sleep Mode in Master Mode” to clarify what occurs when entering
Sleep mode while transmitting.
Updated the slave message RBF status bit information in Figure 7-11 through Figure 7-16.
Additional minor corrections such as language and formatting updates are incorporated
throughout the document.
Revision C (November 2009)
This revision includes the following corrections and updates:
The document was updated to include the PIC24H families of devices
Added Note 1 to the IPMIEN bit in the I2CxCON register (Register 3-1)
Updated the bit status to HSC (Hardware Set/Cleared) for the P and S bits in the I2CxSTAT
register (Register 3-4)
Updated the BRG Reload Value Calculation (Equation 4-1)
Added a shaded note on the SDAx and SCLx pins to Section 2.0 “I
2
C Bus
Characteristics” and Section 8.0 “Connection Considerations for I
2
C Bus”
Added a shaded note after the first paragraph in Section 5.0 “Communicating as a
Master in a Single Master Environment” and Section 6.0 “Communicating as a
Master in a Multi-Master Environment”
Removed the Actual F
SCL column, added the PGD column, and updated the Decimal and
Hexadecimal values in the I
2
C Clock Rates table (Table )
Added a sentence to the end of the second paragraph and added a shaded note in
Section 7.3.8 “Receiving All Addresses (IPMI Operation)”
Added a shaded note to the first paragraph of Section 7.5 “Sending Data to a Master
Device”
Updated the last sentence of the first paragraph in Section 7.5.2 “Example Messages of
Slave Transmission” to clarify that an interrupt will be generated.
Added a shaded note to Section 9.1 “Sleep Mode in Slave Mode”

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