Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

2014 Microchip Technology Inc. DS70005185A-page 27
Serial Peripheral Interface (SPI) Module
3.5.1 FRAME MASTER AND FRAME SLAVE MODES
When SPIFSD (SPIxCON2<14>) = 0, the SPIx module is in Framed Master mode. In this
mode, the frame synchronization pulse is initiated by the module when the user application
writes the transmit data to the SPIxBUF location (writing the SPIxTXB register with transmit
data). At the end of the frame synchronization pulse, the data is transferred from the
SPIxTXB register to the SPIxSR register and data transmission/reception begins.
When SPIFSD = 1, the SPIx module is in Framed Slave mode. In this mode, the frame
synchronization pulse is generated by an external source. When the module samples the
frame synchronization pulse, it transfers the contents of the SPIxTXB register to the
SPIxSR register and data transmission/reception begins. The user application must ensure
that the correct data is loaded into the SPIxBUF register for transmission before the frame
synchronization pulse is received.
3.5.2 SPI MASTER/FRAMED MASTER MODE
In SPI Master/Framed Master mode, the SPIx module generates both the clock and the frame
synchronization signals, as shown in Figure 3-7. This configuration is enabled by setting the
MSTEN and FRMEN bits (SPIxCON1<5> and SPIxCON2<15>) to 1’, and the SPIFSD bit
(SPIxCON2<14>) to ‘0’.
In this mode, the serial clock is output continuously at the SCKx pin, regardless of whether the
module is transmitting. When the SPIxBUF register is written, the SSx
pin is driven to its active
state (as determined by the FRMPOL bit) on the appropriate transmit edge of the SCKx clock
and remains active for one data frame. Figure 3-8 shows that if the FRMDLY control bit
(SPIxCON2<1>) is cleared, the frame synchronization pulse precedes the data transmission.
Figure 3-9 shows that if FRMDLY is set, the frame synchronization pulse coincides with the
beginning of the data transmission. The module starts transmitting data on the next transmit edge
of the SCKx pin.
Figure 3-7: SPIx Master/Framed Master Connection Diagram
Note: Receiving a frame synchronization pulse starts a transmission, regardless of
whether data is written to the SPIxBUF register. If no write operation is performed,
the existing contents of the SPIxTXB register are transmitted.
SDOx
SDIx
dsPIC33/PIC24
Serial Clock
SSx
SCKx
Frame Sync
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
(SPIx Master/Framed Master)

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