Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

2007-2014 Microchip Technology Inc. DS70000195F-page 41
Figure 7-4: I
2
C™ Slave, 7-Bit Address, Reception (STREN = 1, AHEN = 0, DHEN = 0)
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2SDAx
SCLx
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6
SCLREL
I2COV
RBF
ACK
SI2CxIF
1 3 4 5 6 7 8 1110
9
1
Detecting Start bit, enables address detection, interrupt is set if SCEN is set.
3
4
5
9
11
12
RBF is set on the 8th falling clock, address is loaded to I2CxRCV. RBF is asserted.
Interrupt is asserted.
SCLx is stretched low until SCLREL is set.
User software reads the I2CxRCV buffer that clears the RBF flag.
User software releases the SCLx line by writing SCLREL to1’.
Data is loaded into I2CxRCV. RBR flag is asserted.
On the 9th falling clock edge, interrupt is asserted.
SCLx is stretched and held at low until SCLREL is set
User software releases SCLx line by writing SCLREL t
NACK is received (SCLx is not stretched to low).
2
2
User software clears the interrupt flag.
13
Slave recognizes the Stop event.
7
6
8
10
R/W = 0
ACK

e-Highlighter

Click to send permalink to address bar, or right-click to copy permalink.

Un-highlight all Un-highlight selectionu Highlight selectionh