Vault 7: Projects

This publication series is about specific projects related to the Vault 7 main publication.

16-bit MCU and DSC Programmer’s Reference Manual
DS70157F-page 228 © 2005-2011 Microchip Technology Inc.
DIVF
Fractional Divide
Implemented in: PIC24F PIC24H PIC24E dsPIC30F dsPIC33F dsPIC33E
X X X
Syntax: {label:} DIVF Wm, Wn
Operands: Wm [ W0 ... W15]
Wn [ W2 ... W15]
Operation: 0x0 W0
Wm W1
W1:W0/Wn W0
Remainder W1
Status Affected: N, OV, Z, C
Encoding: 1101 1001 0ttt t000 0000 ssss
Description: Iterative, signed fractional 16-bit by 16-bit divide, where the dividend is
stored in Wm and the divisor is stored in Wn. To perform the operation,
W0 is first cleared and Wm is copied to W1. The 16-bit quotient of the
divide operation is stored in W0, and the 16-bit remainder is stored in W1.
The sign of the remainder will be the same as the sign of the dividend.
This instruction must be executed 18 times using the REPEAT instruction
(with an iteration count of 17) to generate the correct quotient and
remainder. The N flag will be set if the remainder is negative and cleared
otherwise. The OV flag will be set if the divide operation resulted in an
overflow and cleared otherwise. The Z flag will be set if the remainder is
0’ and cleared otherwise. The C flag is used to implement the divide
algorithm and its final value should not be used.
The ‘t’ bits select the dividend register.
The ‘s’ bits select the divisor register.
Note 1: For the fractional divide to be effective, Wm must be less than
Wn. If Wm is greater than or equal to Wn, unexpected results
will occur because the fractional result will be greater than or
equal to 1.0. When this occurs, the OV Status bit will be set and
the quotient and remainder should not be used.
2: Dividing by zero will initiate an arithmetic error trap during the
first cycle of execution.
3: This instruction is interruptible on each instruction cycle
boundary.
Words: 1
Cycles: 18 (plus 1 for REPEAT execution)

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